Test chip design and parameter extraction of parasitic capacitance of MOSFET in VLSI

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dc.contributor.authorA. Ruangphanit
dc.contributor.authorR. Pedlub
dc.contributor.authorR. Muanghlua
dc.date.accessioned2025-07-21T05:57:59Z
dc.date.issued2017-03-01
dc.identifier.doi10.1109/ieecon.2017.8075907
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/6354
dc.subjectParasitic capacitance
dc.subjectParasitic extraction
dc.subject.classificationAdvancements in Semiconductor Devices and Circuit Design
dc.titleTest chip design and parameter extraction of parasitic capacitance of MOSFET in VLSI
dc.typeArticle

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