Current mode pulse width modulation/pulse position modulation based on phase lock loop

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dc.contributor.authorWisartpong, Pichet
dc.contributor.authorSilaphan, Vorapong
dc.contributor.authorKurutach, Sunee
dc.contributor.authorWardkein, Paramote
dc.date.accessioned2026-08-06T10:16:33Z
dc.date.available2026-08-06T10:16:33Z
dc.date.issued2017-05-01
dc.description.abstractIn this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 μm CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 μA to 109 μA, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 μm× 60 μm.
dc.identifier.citationJournal of Electrical Engineering, 68(3), 180-187, 2017
dc.identifier.doi10.1515/jee-2017-0026
dc.identifier.issn13353632
dc.identifier.other2-s2.0-85028061962
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/7610
dc.sourceJournal of Electrical Engineering
dc.subjectCurrent mode
dc.subjectPhase lock loop
dc.subjectPulse position modulation
dc.subjectPulse width modulation
dc.titleCurrent mode pulse width modulation/pulse position modulation based on phase lock loop
dc.typeArticle

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