Adaptive equalization architecture using distributed arithmetic for partial response channels

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dc.contributor.authorChivapreecha, Sorawat
dc.contributor.authorJaruvarakul, Aungkana
dc.contributor.authorJaruvarakul, Nivat
dc.contributor.authorDejhan, Kobchai
dc.date.accessioned2026-08-06T09:54:48Z
dc.date.available2026-08-06T09:54:48Z
dc.date.issued2006-12-01
dc.description.abstractThis paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA), which is able to calculate the inner product by shifting, and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high-speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.. © 2006 IEEE.
dc.identifier.citationProceedings of the International Symposium on Consumer Electronics ISCE, 553-557, 2006
dc.identifier.other2-s2.0-34547349031
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/1486
dc.sourceProceedings of the International Symposium on Consumer Electronics ISCE
dc.subjectAdaptive digital filter
dc.subjectDistributed arithmetic
dc.subjectFPGA
dc.subjectLMS algorithm
dc.titleAdaptive equalization architecture using distributed arithmetic for partial response channels
dc.typeConference Paper

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