VLSI architecture of burst mode acceleration for 128-bit block ciphers

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dc.contributor.authorY. Mitsuyama
dc.contributor.authorZ. Andales
dc.contributor.authorT. Onoye
dc.contributor.authorI. Shirakawa
dc.contributor.authorI. Arungsrisangchai
dc.date.accessioned2025-07-21T05:47:36Z
dc.date.issued2003-06-25
dc.identifier.doi10.1109/iscas.2002.1010995
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/478
dc.subjectBlock size
dc.subjectPlain text
dc.subject.classificationCryptographic Implementations and Security
dc.titleVLSI architecture of burst mode acceleration for 128-bit block ciphers
dc.typeArticle

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