8 bit presettable/programmable synchronous counter/divider

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dc.contributor.authorChoomchuay, Somsak
dc.contributor.authorSupadech, Somkiat
dc.contributor.authorSangworasilp, Manus
dc.date.accessioned2026-08-06T09:49:47Z
dc.date.available2026-08-06T09:49:47Z
dc.date.issued1989-12-01
dc.description.abstractThe authors describe the design and implementation of an ASIC (application-specific integrated circuit) chip. The design is a J-K flip-flop-based counter. With appropriate control circuitry, this chip can function as a multimode counter/divider subsystem. The device was fabricated using a 5-μm p-well polysilicon-gate CMOS process. It is noted that, due to its versatility, this ASIC has many potential applications.
dc.identifier.citationundefined, 230-233, 1989
dc.identifier.other2-s2.0-0024908424
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/79
dc.sourceundefined
dc.title8 bit presettable/programmable synchronous counter/divider
dc.typeConference Paper

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