Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient

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dc.contributor.authorA. Thanachayanont
dc.date.accessioned2026-05-08T19:18:15Z
dc.date.issued2022-3-21
dc.identifier.doi10.1007/s10470-022-02023-0
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/16416
dc.publisherAnalog Integrated Circuits and Signal Processing
dc.subjectAnalog and Mixed-Signal Circuit Design
dc.subjectCCD and CMOS Imaging Sensors
dc.subjectRadio Frequency Integrated Circuit Design
dc.titleDesign procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient
dc.typeArticle

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