A new model for predicting the effect of temperature and devices dimension on threshold voltage of PMOS in VLSI

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dc.contributor.authorA. Ruangphanit
dc.contributor.authorA. Poyai
dc.contributor.authorN. Sakuna
dc.contributor.authorS. Niemcharoen
dc.contributor.authorR. Muanghlua
dc.date.accessioned2025-07-21T05:55:55Z
dc.date.issued2015-06-01
dc.identifier.doi10.1109/ecticon.2015.7206949
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/5175
dc.subjectNegative-bias temperature instability
dc.subjectTemperature coefficient
dc.subjectOverdrive voltage
dc.subject.classificationAdvancements in Semiconductor Devices and Circuit Design
dc.titleA new model for predicting the effect of temperature and devices dimension on threshold voltage of PMOS in VLSI
dc.typeArticle

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