Performance estimates of an embedded CPU for high-speed packet processing

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dc.contributor.authorTomoaki Sato
dc.contributor.authorPhichet Moungnoul
dc.contributor.authorSorawat Chivapreecha
dc.contributor.authorKohji Higuchi
dc.date.accessioned2025-07-21T05:54:53Z
dc.date.issued2014-05-01
dc.identifier.doi10.1109/ecticon.2014.6839849
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/4581
dc.subjectCPU shielding
dc.subjectPacket processing
dc.subjectNetwork processor
dc.subject.classificationWireless Networks and Protocols
dc.titlePerformance estimates of an embedded CPU for high-speed packet processing
dc.typeArticle

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