Throughput of a firewall unit on FPGAs developed by the RTL design methodology

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dc.contributor.authorTomoaki Sato
dc.contributor.authorSorawat Chivapreecha
dc.contributor.authorPhichet Moungnoul
dc.contributor.authorKohji Higuchi
dc.date.accessioned2025-07-21T05:57:59Z
dc.date.issued2017-03-01
dc.identifier.doi10.1109/ieecon.2017.8075819
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/6359
dc.subjectFirewall (physics)
dc.subjectDesign methods
dc.subject.classificationNetwork Packet Processing and Optimization
dc.titleThroughput of a firewall unit on FPGAs developed by the RTL design methodology
dc.typeArticle

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