An FPGA-based implementation of variable fractional delay filter

Simple item page
dc.contributor.authorUssanai Nithirochananont
dc.contributor.authorSorawat Chivapreecha
dc.contributor.authorKobchai Dejhan
dc.date.accessioned2025-07-21T05:50:28Z
dc.date.issued2009-03-01
dc.identifier.doi10.1109/cspa.2009.5069197
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/2060
dc.subjectFinite impulse response
dc.subject.classificationDigital Filter Design and Implementation
dc.titleAn FPGA-based implementation of variable fractional delay filter
dc.typeArticle

Files

Collections

All