Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient

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dc.contributor.authorApinunt Thanachayanont
dc.date.accessioned2025-07-21T06:06:53Z
dc.date.issued2022-03-21
dc.identifier.doi10.1007/s10470-022-02023-0
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/11203
dc.subjectTransconductance
dc.subjectOperational transconductance amplifier
dc.subjectCascode
dc.subject.classificationAnalog and Mixed-Signal Circuit Design
dc.titleDesign procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient
dc.typeArticle

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