Simple design technique for realizing low-voltage low-power CMOS current multiplier

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dc.contributor.authorTangjit, Jetwara
dc.contributor.authorTangsrirat, Worapong
dc.contributor.authorSatansup, Jetsdaporn
dc.contributor.authorSurakampontorn, Wanlop
dc.date.accessioned2026-08-06T10:10:24Z
dc.date.available2026-08-06T10:10:24Z
dc.date.issued2015-01-01
dc.description.abstractA simple circuit design technique for the realization of compact low-voltage low-power CMOS four-quadrant analog current multiplier circuit has been suggested. It is based on the use of the square-law characteristic in the NMOS current squaring function circuit operating in the saturation region. The suggested four-quadrant current multiplier circuit is designed for implementing in TSMC 0.25-μm CMOS technology with a low supply voltage of ±0.75V. To evaluate the circuit performance, the circuit has been simulated by PSPICE program. The simulation results show that the circuit has a linearity error of about 1%, a THD of 1.07% at 100 kHz, the total power consumption of 87.6 μW and -3dB bandwidth of 1.32 GHz.
dc.identifier.citationProceedings 2015 7th International Conference on Information Technology and Electrical Engineering Envisioning the Trend of Computer Information and Engineering Icitee 2015, 110-113, 2015
dc.identifier.doi10.1109/ICITEED.2015.7408923
dc.identifier.other2-s2.0-84966601364
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/5936
dc.sourceProceedings 2015 7th International Conference on Information Technology and Electrical Engineering Envisioning the Trend of Computer Information and Engineering Icitee 2015
dc.subjectCMOS analog circuits
dc.subjectcurrent multiplier
dc.subjectcurrent squarer
dc.subjectcurrent-mode circuit
dc.titleSimple design technique for realizing low-voltage low-power CMOS current multiplier
dc.typeConference Paper

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