A hardware design of MS/MMS-based LDPC decoder

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dc.contributor.authorItsara Tanyanon
dc.contributor.authorSomsak Choomchuay
dc.date.accessioned2025-07-21T05:53:25Z
dc.date.issued2012-12-01
dc.identifier.doi10.1109/edssc.2012.6482804
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/3724
dc.subjectVerilog
dc.subjectParity-check matrix
dc.subjectSoft-decision decoder
dc.subject.classificationError Correcting Code Techniques
dc.titleA hardware design of MS/MMS-based LDPC decoder
dc.typeArticle

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