1.5-V CMOS current multiplier/divider

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dc.contributor.authorSatansup, Jetsdaporn
dc.contributor.authorTangsrirat, Worapong
dc.date.accessioned2026-08-06T10:19:56Z
dc.date.available2026-08-06T10:19:56Z
dc.date.issued2018-06-01
dc.description.abstractA circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-μm CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 μW, and -3dB small-signal frequency of about 245 MHz.
dc.identifier.citationInternational Journal of Electrical and Computer Engineering, 8(3), 1478-1487, 2018
dc.identifier.doi10.11591/ijece.v8i3.pp1478-1487
dc.identifier.issn20888708
dc.identifier.other2-s2.0-85066271070
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/8570
dc.sourceInternational Journal of Electrical and Computer Engineering
dc.subjectAnalog multiplier
dc.subjectCurrent-mode circuit
dc.subjectLow voltage
dc.subjectMOS analog circuits
dc.subjectSquarer
dc.title1.5-V CMOS current multiplier/divider
dc.typeArticle

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