RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation

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dc.contributor.authorSato, Tomoaki
dc.contributor.authorChivapreecha, Sorawat
dc.contributor.authorMoungnoul, Phichet
dc.contributor.authorHiguchi, Kohji
dc.date.accessioned2026-08-06T10:14:12Z
dc.date.available2026-08-06T10:14:12Z
dc.date.issued2016-09-06
dc.description.abstractField-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.
dc.identifier.citation2016 13th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2016, 2016
dc.identifier.doi10.1109/ECTICon.2016.7561415
dc.identifier.other2-s2.0-84988891952
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/6981
dc.source2016 13th International Conference on Electrical Engineering Electronics Computer Telecommunications and Information Technology Ecti Con 2016
dc.subjectFPGAs
dc.subjectRCA
dc.subjectRTL design methodology
dc.subjectSoC
dc.subjectwave-pipeline
dc.titleRCA on FPGAs designed by the RTL design methodology and wave-pipelined operation
dc.typeConference Paper

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