An efficient algorithm for circuit partitioning

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dc.contributor.authorYodtean, Apiradee
dc.contributor.authorChoomchuay, Somsak
dc.contributor.authorSuzuki, Yasoji
dc.date.accessioned2026-08-06T09:50:29Z
dc.date.available2026-08-06T09:50:29Z
dc.date.issued1999-12-01
dc.description.abstractThis paper describes an improved simulated annealing algorithm applied for graph balanced bipartitioning problem, in particular for circuit partitioning problem. The new algorithm has incorporated the idea and procedure required in a genetic algorithm Experiment results on industrial benchmark circuits show that the proposed algorithm is superior to a conventional simulated annealing algorithm in both cut cost and run time.
dc.identifier.citationInternational Symposium on IC Technology Systems and Applications, 8, 359-362, 1999
dc.identifier.other2-s2.0-1842627607
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/249
dc.sourceInternational Symposium on IC Technology Systems and Applications
dc.titleAn efficient algorithm for circuit partitioning
dc.typeConference Paper

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