A 32 bits architecture for an AES system

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dc.contributor.authorS. Pongyupinpanich
dc.contributor.authorS. Phathumvanh
dc.contributor.authorS. Choomchuay
dc.date.accessioned2025-07-21T05:48:01Z
dc.date.issued2005-04-12
dc.identifier.doi10.1109/iscit.2004.1412452
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/699
dc.subjectNIST
dc.subjectDisk encryption hardware
dc.subjectAES implementations
dc.subject.classificationCryptographic Implementations and Security
dc.titleA 32 bits architecture for an AES system
dc.typeArticle

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