Optimization of multithread for long digit multiplier: By using ancient India Vedic mathematic

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dc.contributor.authorNopphagaw Thongbai
dc.contributor.authorPanwit Tuwanuti
dc.date.accessioned2025-07-21T05:58:19Z
dc.date.issued2017-06-01
dc.identifier.doi10.1109/ecticon.2017.8096322
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/6521
dc.subjectNumerical digit
dc.subject.classificationLow-power high-performance VLSI design
dc.titleOptimization of multithread for long digit multiplier: By using ancient India Vedic mathematic
dc.typeArticle

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