A DXCCII-based four-quadrant multiplier

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dc.contributor.authorKumngern, Montree
dc.date.accessioned2026-08-06T10:07:04Z
dc.date.available2026-08-06T10:07:04Z
dc.date.issued2013-08-28
dc.description.abstractThis paper presents a four-quadrant analog multiplier using dual-X second-generation current conveyors (DXCCIIs). The proposed multiplier employs only two DXCCIIs and eight MOS transistors operating in saturation region, which is ideal for monolithic implementation. The use of MOS devices operating in saturation region offers high-frequency capability of the circuit. PSPICE simulators using 0.35 μm TSMC CMOS process are used to validate the workability of the circuit. Simulation results show that the circuit has a -3dB bandwidth of 450 MHz, 1.59 % total harmonic distortion for the input current 200 mVP-P. © 2013 IEEE.
dc.identifier.citationProceedings of the 2013 IEEE 7th International Power Engineering and Optimization Conference Peoco 2013, 738-741, 2013
dc.identifier.doi10.1109/PEOCO.2013.6564644
dc.identifier.other2-s2.0-84882766054
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/4985
dc.sourceProceedings of the 2013 IEEE 7th International Power Engineering and Optimization Conference Peoco 2013
dc.subjectanalog multiplier
dc.subjectanalog signal processing
dc.subjectdual-X second-generation current conveyor (DXCCII)
dc.titleA DXCCII-based four-quadrant multiplier
dc.typeConference Paper

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