Configurable Hardware Architecture of Multidimensional Convolution Coprocessor

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dc.contributor.authorBoonyuu, Geranun
dc.contributor.authorWisayataksin, Sumek
dc.date.accessioned2026-08-06T10:31:48Z
dc.date.available2026-08-06T10:31:48Z
dc.date.issued2021-01-20
dc.description.abstractWe propose a configurable coprocessor for the convolutional neural network (CNN) that suit various models of CNN. It can operate 2D standard convolution, 2D depthwise separable convolution, 3D convolution, and a fully connected layer. The proposed processing cluster consists of 72 processing units (PUs) of half-precision floating-point to assist the main processor in embedded systems. The experimental results on Artix-7 FPGA revealed that our design has 12.16 GOPs per cluster. Moreover, this architecture was designed to be scalable for the systems with higher performance.
dc.identifier.citation2021 2nd International Symposium on Instrumentation Control Artificial Intelligence and Robotics Ica Symp 2021, 2021
dc.identifier.doi10.1109/ICA-SYMP50206.2021.9358447
dc.identifier.other2-s2.0-85102502881
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/11822
dc.source2021 2nd International Symposium on Instrumentation Control Artificial Intelligence and Robotics Ica Symp 2021
dc.subject3D convolution
dc.subjectConvolutional Neural network
dc.subjectDepthwise Separable Convolution
dc.subjectEmbedded Systems
dc.subjectFPGA
dc.titleConfigurable Hardware Architecture of Multidimensional Convolution Coprocessor
dc.typeConference Paper

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