Search algorithm of write voltage optimization in NAND flash memory

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dc.contributor.authorDuangthong, Chatuporn
dc.contributor.authorPhakphisut, Watid
dc.contributor.authorSupnithi, Pornchai
dc.date.accessioned2026-08-06T10:17:29Z
dc.date.available2026-08-06T10:17:29Z
dc.date.issued2017-10-19
dc.description.abstractIn NAND flash memory, the major problem is voltage immigration which is the result of program and erase (PE) cycling number and data retention time. Although previous works study the write voltage optimization for NAND flash memory, the write voltage optimization of multilevel coding (MLC) and bitinterleaved coded modulation (BICM) structure have not been focused, therefore, in this work, we propose the search algorithm of write voltage optimization for MLC and BICM structure. The search algorithm can reduce the number of possible write voltages and provides the optimal write voltage for each PE cycling number. The bit-error rate (BER) performance of optimized write voltage is lower than the fixed write voltage in BICM structure. Moreover, the proposed optimization technique provides the most significant bit (MSB) and least significant bit (LSB) of MLC structure with identical BER performances.
dc.identifier.citation2017 International Electrical Engineering Congress Ieecon 2017, 2017
dc.identifier.doi10.1109/IEECON.2017.8075860
dc.identifier.other2-s2.0-85039956306
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/7877
dc.source2017 International Electrical Engineering Congress Ieecon 2017
dc.subjectBICM
dc.subjectMLC
dc.subjectNAND flash memory
dc.subjectWrite voltage optimization
dc.titleSearch algorithm of write voltage optimization in NAND flash memory
dc.typeConference Paper

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