Design of High Performance and Low Cost Line Impedance Stabilization Network for University Power Electronics and EMC Laboratories

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dc.contributor.authorD. Sakulhirirak
dc.contributor.authorV. Tarateeraseth
dc.contributor.authorW. Khan-ngern
dc.contributor.authorN. Yoothanom
dc.date.accessioned2025-07-21T05:49:23Z
dc.date.issued2007-11-01
dc.identifier.doi10.1109/peds.2007.4487715
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/1445
dc.subjectPower Electronics
dc.subjectElectromagnetic Compatibility
dc.subject.classificationElectromagnetic Compatibility and Noise Suppression
dc.titleDesign of High Performance and Low Cost Line Impedance Stabilization Network for University Power Electronics and EMC Laboratories
dc.typeArticle

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