A low voltage four-quadrant analog multiplier using triode-MOSFETs

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dc.contributor.authorKiatwarin, N.
dc.contributor.authorSawigun, C.
dc.contributor.authorKiranon, W.
dc.date.accessioned2026-08-06T09:54:29Z
dc.date.available2026-08-06T09:54:29Z
dc.date.issued2006-12-01
dc.description.abstractA low voltage four-quadrant analog multiplier circuit is presented. Based on triode region operation of MOSFET, the multiplier circuit can be simply realized by connecting a pair of PMOS with three flipped voltage follower circuits. As a result, the proposed circuit is compact and can be operated under low voltage supply. Circuit simulation using SPICE with 0.35 micron CMOS model parameter shows that under 1.5V single supply the proposed multiplier provides linear range of more than 50% of voltage supply (measured from THD less than 1%) and small signal bandwidth is higher than 95MHz while the entire circuit consumes 46.4 μW of electrical power. © 2006 IEEE.
dc.identifier.citation2006 International Symposium on Communications and Information Technologies Iscit, 1105-1108, 2006
dc.identifier.doi10.1109/ISCIT.2006.339950
dc.identifier.other2-s2.0-50949107429
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/1402
dc.source2006 International Symposium on Communications and Information Technologies Iscit
dc.titleA low voltage four-quadrant analog multiplier using triode-MOSFETs
dc.typeConference Paper

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