Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints

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dc.contributor.authorChantana Chantrapornchai
dc.contributor.authorWanlop Surakumpolthorn
dc.contributor.authorEdwin Sha
dc.date.accessioned2025-07-21T05:47:46Z
dc.date.issued2004-01-01
dc.identifier.doi10.1007/978-3-540-30121-9_25
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/551
dc.subjectRegister allocation
dc.subject.classificationManufacturing Process and Optimization
dc.titleEfficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints
dc.typeBook chapter

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