VLSI architecture of digital matched filter and prime interleaver for W-CDMA

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dc.contributor.authorY. Uchida
dc.contributor.authorM. Ise
dc.contributor.authorT. Onoye
dc.contributor.authorI. Shirakawa
dc.contributor.authorI. Arungsrisangchai
dc.date.accessioned2025-07-21T05:47:36Z
dc.date.issued2003-06-25
dc.identifier.doi10.1109/iscas.2002.1010212
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/479
dc.subject.classificationAdvanced Wireless Communication Techniques
dc.titleVLSI architecture of digital matched filter and prime interleaver for W-CDMA
dc.typeArticle

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