Analog operation in CMOS latch circuit for reducing dynamic power dissipation

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dc.contributor.authorDejhan, K.
dc.contributor.authorCheevasuvit, F.
dc.contributor.authorTipsuwanporn, V.
dc.contributor.authorTrisuwannawat, T.
dc.contributor.authorPrommas, E.
dc.date.accessioned2026-08-06T09:49:52Z
dc.date.available2026-08-06T09:49:52Z
dc.date.issued1992-01-01
dc.description.abstractMany approaches to study of analog operation in CMOS VLSI. This paper is focused on finding an analog operation using pMOS transistor which is used to control the variation of dynamic power dissipation of the CMOS static latch circuit. The results have been simulated using SPICE under 1.2μm HCMOS3 technology.
dc.identifier.citationMidwest Symposium on Circuits and Systems, 1992-August, 544-547, 1992
dc.identifier.doi10.1109/MWSCAS.1992.271266
dc.identifier.issn15483746
dc.identifier.other2-s2.0-85065711784
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/93
dc.sourceMidwest Symposium on Circuits and Systems
dc.titleAnalog operation in CMOS latch circuit for reducing dynamic power dissipation
dc.typeConference Paper

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