Design of combinational logic training system using FPGA

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dc.contributor.authorSujittra Sothong
dc.contributor.authorPornpimon Chayratsami
dc.date.accessioned2025-07-21T05:51:32Z
dc.date.issued2010-10-01
dc.identifier.doi10.1109/fie.2010.5673663
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/2679
dc.subjectCombinational logic
dc.subjectProgrammable logic array
dc.subjectRegister-transfer level
dc.subjectGate array
dc.subjectSequential logic
dc.subject.classificationExperimental Learning in Engineering
dc.titleDesign of combinational logic training system using FPGA
dc.typeArticle

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