Interpretation Petri net model to IEC 1131-3: LD for programmable logic controller

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dc.contributor.authorT. Suesut
dc.contributor.authorP. Inban
dc.contributor.authorP. Nilas
dc.contributor.authorP. Rerngreun
dc.contributor.authorS. Gulphanich
dc.date.accessioned2025-07-21T05:48:08Z
dc.date.issued2005-06-15
dc.identifier.doi10.1109/ramech.2004.1438074
dc.identifier.urihttps://dspace.kmitl.ac.th/handle/123456789/742
dc.subjectLadder logic
dc.subjectFunction block diagram
dc.subject.classificationPetri Nets in System Modeling
dc.titleInterpretation Petri net model to IEC 1131-3: LD for programmable logic controller
dc.typeArticle

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