A CMOS log-antilog current multiplier/divider circuit using DDCC - Torteanchai, Usa; Kumngern, Montree; Dejhan, Kobchai (My University, 2011)
This paper presents a new one-quadrant analog log-antilog multiplier/divider using only one differential different current conveyor and four diodes. The proposed circuit features low circuit complexity, very suitable for integrated circuit implementation and excellent temperature stability. Simulation results show performance of the circuit and confirm the validity of the proposed design technique. © 2011 IEEE.
Keywords: CMOS; differential difference current conveyor; log-antilog multiplier