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Digital technique to generate variable and multiple PWM signals
(2007-01-01)
Pongswatd, Sawai
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Chaikla, Amphawan
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Ukakimapurn, Prapart
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Tirasesth, Kitti
In this paper, we present a digital technique to generate Pulse Width Modulation (PWM) signal using counters, comparators, and latching circuits implemented by Verilog HDL program based on FPGA. The proposed technique can simultaneously generate variable and multiple PWM outputs with parallel processing. Setting each reference-input signal can independently and easily vary the pulse width of each generated signal. The FPGA-based implementation can minimize the size of hardware. The communication can be easily done via a personnel computer. Application example in the design of the proposed technique as the parallel processing is also included. © 2007 IEEE.
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A simple voltage controlled oscillator using bootstrap circuits and NOR-RS flip flop
(2007-01-01)
Chaikla, Amphawan
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Pongswatd, Sawai
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Sasaki, Hirofumi
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Fujimoto, Kuniaki
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Yahara, Mitsutoshi
This paper presents a simple and successful design for a voltage controlled oscillator. The proposed circuit is based on the use of two identical bootstrap circuits and a NOR-RS Flip Flop to generate wide-tunable sawtooth and square waves. Increasing control voltage linearly increases the output oscillation frequency. Experimental results verifying the performances of the proposed circuit are in agreement with the calculated values.
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An amplitude detector for variable frequency sinusoidal signals
(2006-12-01)
Raksachat, Pariwat
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Chaikla, Amphawan
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Kaewpoonsuk, Anucha
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Riewruja, Vanchai
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Julsereewong, Prasit
In this paper, a JK-flip-flop-based logic circuit is described. Using two output signals of this designed logic circuit to control a buffered peak detector followed by a simple sample-and-hold circuit in sequential operation, a sinusoidal amplitude detector is proposed. The proposed detector allows the frequency of input signals to be varied over a wide range. Experimental results verifying the performances of the proposed circuit are in close agreement with the expected values. © 2006 ICASE.
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OTA-based gray-code algorithmic ADC
(2006-12-01)
Chaikla, Amphawan
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Arayawat, Somjai
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Riewruja, Vanchai
This paper presents a Gray-code algorithmic analog-to-digital converter (ADC). The proposed circuit comprises of OTAs, diodes, resistors, and voltage comparator to synthesize a triangular-like DC transfer characteristic and a digital output for an one-bit cell ADC. The design structure is simple and flexible. An N-bit resolution can be implemented by cascading the N proposed one-bit cells. Experimental results verifying the circuit performances are agreed with the theoretical values. © 2006 ICASE.
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A CMOS-based multiple-input max/min circuit
(2005-12-01)
Keawconthai, Supatpong
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Wangwiwattana, Chaleompun
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Chaikla, Amphawan
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Riewruja, Vanchai
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Julsereewong, Prasit
This paper presents a CMOS circuit technique for realization of the current-mode multiple-input Max/Min circuit. The maximum and minimum functions are incorporated into the same scheme with parallel processing. The design strategy is based on the use of MOS transistor operating at the edge of conduction. The proposed circuit performs a low-distortion in the transfer characteristic and is useful building block for the real-time systems. The performances of the proposed circuit were studied using the PSFICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values. © 2005 IEEE.
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A low-voltage algorithmic ADC based on gray coding
(2004-12-27)
Arayawat, Somjai
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Chaikla, Amphawan
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Riewruja, Vanchai
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Julsereewong, Prasit
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Trisuwannawat, Thanit
This paper presents an algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of the De Morgan's law-based two-input minimum circuit, which performs a low-distortion in the transfer characteristic. The proposed ADC with the low supply voltage is simple, small in size and suitable for implementing a high-resolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.
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An analog current-mode multiple-input max/min circuit
(2004-12-27)
Keawconthai, Supatpong
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Masuchun, Ruedee
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Chaikla, Amphawan
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Riewruja, Vanchai
;
Julsereewong, Prasit
This paper presents an analog modular multiple-input Max/Min circuit, which operates in the current-mode. The maximum and minimum functions are incorporated into the same scheme with parallel processing. The realization method is suitable for fabrication using CMOS technology. The proposed circuit has a very sharp transfer characteristic and is useful building block for the real-time systems. The performances of the proposed Max/Min circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.
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A high-speed algorithmic ADC
(2004-12-01)
Riewruja, Vanchai
;
Chaikla, Amphawan
A method for realizing high-speed algorithmic analogue-to-digital converter (ADC) is presented in this paper. The realization method based on the proposed absolute function circuit, which performs a low-distortion in the transfer characteristic, is utilized. The proposed ADC is simple, small in size and suitable for implementing a high-resolution ADC. Performances of the proposed circuit are discussed in detail and confirmed through Cadence Spectre simulation results.
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An analog current-mode multiple-input Max/min circuit
(2004-11-17)
Keawconthai, Supatpong
;
Masuchun, Ruedee
;
Chaikla, Amphawan
;
Riewruja, Vanchai
;
Julsereewong, Prasit
This paper presents an analog modular multiple-input Max/Min circuit, which operates in the current-mode. The maximum and minimum functions are incorporated into the same scheme with parallel processing. The realization method is suitable for fabrication using CMOS technology. The proposed circuit has a very sharp transfer characteristic and is useful building block for the real-time systems, The performances of the proposed Max/Min, circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.
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A low-voltage algorithmic ADC based on gray coding
(2004-11-17)
Arayawat, Somjai
;
Chaikla, Amphawan
;
Riewruja, Vanchai
;
Julsereewong, Prasit
;
Trisuwannawat, Thanit
This paper presents an algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of the De Morgan's law-based two-input minimum circuit, which performs a low-distortion in the transfer characteristic. The proposed ADC with the low supply voltage is simple, small in size and suitable for implementing a high-resolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.

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