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    Low-complexity based TDE Method for OFDM signal in higher time-varying fading channels
    (2020-01-01)
    Tanangsanakool, Saha
    ;
    Reangsuntea, Pongsathorn
    ;
    Mori, Kazuo
    ;
    Boonsrimuang, Pisit
    Orthogonal Frequency Division Multiplexing (OFDM) signal would be damaged significantly by inter-carrier interference (ICI) in higher time-varying fading channels. The ICI leads to fatal degradation of bit error rate (BER) performance due to the loss of orthogonality among subcarriers. To solve this problem, this paper proposes a high accuracy time-domain channel impulse response (CIR) estimation method and low-complexity based time-domain equalization (TDE) method for solving the simultaneous equations instead of using an inverse matrix calculation which can achieve better BER performance and lower computation complexity even in higher time-varying fading channels. The salient features of proposed method are to employ a time-domain training sequence (TS) in the estimation of channel impulse response (CIR) instead of using pilot subcarriers in the frequency domain and to employ the time domain equalization (TDE) method with maximum likelihood (ML) estimation instead of using a conventional frequency domain equalization (FDE) method. This paper also proposes a low-complexity iterative method for solving the simultaneous equations instead of using an inverse matrix calculation, which remains the computation complexity up to 7.8% of inverse matrix calculation with the same BER performance but achieves the BER performance when compared with the conventional method. This paper presents various simulation results in higher time-varying fading channels (vehicle speed ≈ 381 km/hrs) to demonstrate the effectiveness of the proposed method as compared with conventional FDE and TDE methods.
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    Iterative based ML demodulation method for OFDM signal under higher mobile environments
    (2015-07-01)
    Reangsuntea, Pongsathorn
    ;
    Hourai, Mio
    ;
    Mori, Kazuo
    ;
    Boonsrimuang, Pisit
    ;
    Kobayashi, Hideo
    Orthogonal Frequency Division Multiplexing (OFDM) signal would be damaged significantly by inter- carrier interference (ICI) in higher time-varying fading channels which leads fatal degradation of bit error rate (BER) performance due to the loss of orthogonality among subcarriers. To solve this problem, this paper proposes an iterative based maximum likelihood demodulation (MLD) method which can achieve better BER performance with lower computation complexity even in higher time-varying fading channels. The features of proposed method are to employ a time domain training sequence (TS) in the estimation of channel impulse response (CIR) instead of using pilot subcarriers in the frequency domain and to employ a time domain equalization (TDE) method with a maximum likelihood (ML) estimation instead of using a conventional frequency domain equalization (FDE) method. This paper also proposes a low-complexity iterative method for solving the simultaneous equations in the MLD method instead of using an inverse matrix calculation. This paper presents various simulation results in higher time-varying fading channels to demonstrate the effectiveness of proposed method as comparing with the conventional frequency domain equalization method.
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    A FPGA design of AES core architecture for portable hard disk
    (2011-07-21)
    Thongkhome, Khanob
    ;
    Thanavijitpun, Chalermwat
    ;
    Choomchuay, Somsak
    This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of 5 Gbps (USB3.0). We proposed the 128 bits data path of two different AES architectures design, Basic Iterative AES, which reuses the same hardware for all the ten iterations and, One Stage Sub Pipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely 128 bits data path architecture that different from the previous public paper. The implementation result on the targeted FPGA, the basic iterative AES encryption can offer the throughput of 3.85 Gbps at 300 MHz and one stage sub pipelined AES can offer the throughput to increase the efficiency of 6.2 Gbps at 481 MHz clock speed. © 2011 IEEE.