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    A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications
    (2018-06-30)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18μm CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027mm<sup>2</sup>. The overall circuit consumes 9.75μW from a single 1.5V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80dB input dynamic range (from 10μV to 100mV), a bandwidth of 4Hz-10kHz, and a total input-referred noise of 5.52μV.
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    A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
    (2015-08-06)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a programmable 4<sup>th</sup>-order bandpass filter for biomedical applications in a standard 0.18 μm CMOS technology. The center frequency is adjustable from 80 Hz to 7 KHz, using a 6-bit digital-to-analog-converter (DAC). At a center frequency of 1 KHz and quality factor of 4, the simulated dynamic range is 53.6 dB for 1% total harmonic distortion (THD) and the simulated total input-referred noise, integrated from 875 Hz to 1.125 KHz, is 177μV. The filter consumes only 6 nW from a 1-V single power supply voltage.
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    A 1.3-V, 9.1μW wide-dynamic range logarithmic amplifier for cochlear implant system
    (2014-01-01)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a low-noise, low-power, wide-dynamic-range CMOS logarithmic amplifier for cochlear implant system in a standard 0.18μm CMOS technology. The proposed logarithmic amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. The overall circuit consumes only 9.1 μW from a 1.3 V single power supply voltage. The simulated input dynamic range is 80 dB, which covers the input amplitudes ranging from 10 μV to 100 mV. The simulated bandwidth of the amplifier is from 50 Hz to 24 kHz. The simulated total input-referred noise is 4.81 μV, integrated from 100 Hz to 10 kHz. © 2014 IEEE.