KMITL

Permanent URI for this communityhttps://dspace.kmitl.ac.th/handle/123456789/1

Browse

Settings

Author: search.filters.author.Chaikla, AmphawanSubject: search.filters.subject.Peak detector

Search Results

Now showing 1 - 1 of 1
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    An amplitude detector for variable frequency sinusoidal signals
    (2006-12-01)
    Raksachat, Pariwat
    ;
    Chaikla, Amphawan
    ;
    Kaewpoonsuk, Anucha
    ;
    Riewruja, Vanchai
    ;
    Julsereewong, Prasit
    In this paper, a JK-flip-flop-based logic circuit is described. Using two output signals of this designed logic circuit to control a buffered peak detector followed by a simple sample-and-hold circuit in sequential operation, a sinusoidal amplitude detector is proposed. The proposed detector allows the frequency of input signals to be varied over a wide range. Experimental results verifying the performances of the proposed circuit are in close agreement with the expected values. © 2006 ICASE.