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Author: search.filters.author.Kamsri, ThawatchaiSubject: search.filters.subject.Current-mode

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    Item type:Publication,
    A current signal CMOS sample-and-hold circuit
    (2007-12-01)
    Luangpol, Amata
    ;
    Petchmaneelumka, Wandee
    ;
    Kamsri, Thawatchai
    ;
    Riewruja, Vanchai
    This article presents a current signal sample-and-hold (S/H) circuit using 0.5μm CMOS technology. A current minimum circuit is used to sample the input signal in place of a sampling switch used in the conventional S/H circuit. The current peak detector is used to hold the signal from the minimum circuit in the "hold" state. The proposed configuration is adopted effectively to cancel switch feedthrough error. The performances of the proposed circuit are demonstrated using the PSPICE analog simulation program. Simulation results show the sampling frequency up to 100MHz and high accuracy. © ICROS.
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    A current-mode CMOS sample-and-hold circuit for ADC
    (2006-12-01)
    Mahatthumthanant, Phinet
    ;
    Kamsri, Thawatchai
    ;
    Petchmaneelumka, Wandee
    ;
    Sungkabunchoo, Tiparat
    ;
    Riewruja, Vanchai
    This paper presents a current-mode sample-and-hold circuit using 0.5μm CMOS technology. The input signal is sampled using a current subtracter and a half wave rectifier instead of a sampling switch used in the conventional sample-and-hold circuit. As a result, the switch feedthrough error is eliminated. The proposed circuit achieves high sampling frequency up to 100MHz and high accuracy. The performances of the proposed circuit are demonstrated by PSPICE simulation results. © 2006 ICASE.