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0.3-V, 357.4-nW Voltage-Mode First-Order Analog Filter Using a Multiple-Input VDDDA
(2023-01-01)
Khateb, Fabian
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Kumngern, Montree
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Kulej, Tomasz
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Stopjakova, Viera
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Psychalinos, Costas
In this paper, a new versatile first-order voltage-mode analog filter using a single multiple-input voltage differencing differential difference amplifier for extremely low-voltage supply and low-frequency applications is presented. Using multiple-input MOS transistor technique, the filter can realize the first-order transfer functions of non-inverting and inverting low-pass, high-pass, and all-pass filters in a single topology with high input and low output impedance. This is particularly useful for voltage-mode circuits. The filter's pole frequency can be controlled electronically. The filter was used to implement a new quadrature oscillator to confirm its advantages. The multiple-input was applied to bulk-driven differential pairs operating in weak inversion; therefore, the proposed circuit operated from a supply voltage of 0.3 V and consumed 357.4 nW. The circuit was designed in the Cadence program using 0.13m UMC CMOS technology. The performance and robustness of the design was validated by intensive simulations, including Monte Carlo and Process, Voltage and Temperature corner analyses.
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Multiple-Input Universal Filter and Quadrature Oscillator Using Multiple-Input Operational Transconductance Amplifiers
(2021-01-01)
Kumngern, Montree
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Khateb, Fabian
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Kulej, Tomasz
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Psychalinos, Costas
This paper presents a new multiple-input single -output voltage-mode universal biquad filter based on multiple-input operational transconductance amplifiers (MI-OTA). This work demonstrates that the multiple-input OTA-based universal filter can provide more filtering responses and other benefits, compared to conventional OTA-based one. The filter provides electronic and orthogonal control of the natural frequency and the quality factor. Furthermore, a two-phase quadrature oscillator can be obtained by slightly modifying the proposed universal filter while the condition and frequency of oscillation can be controlled orthogonally and electronically. The performance of the proposed circuit is evaluated in Cadence environment using the TSMC $0.18~\mu \text{m}$ CMOS technology. The voltage supply is 1.2 V and the power dissipation of the MI-OTA is $24~\mu \text{W}$. For 1% third intermodulation distortion (IMD3) the dynamic range of the band-pass filter is 78.6 dB. In addition, the proposed filter and oscillator are investigated through experiment tests using LM13700 commercially available OTA.
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0.5 V Universal Filter Based on Multiple-Input FDDAs
(2019-12-01)
Khateb, Fabian
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Kumngern, Montree
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Kulej, Tomasz
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Psychalinos, Costas
This brief presents a universal filter based on multiple-input fully differential difference amplifier (FDDA) that is suitable for extremely low-power low-voltage applications. The filter employs three FDDAs, eight resistors, four capacitors and can provide low-pass, band-pass, high-pass, band-stop and all-pass voltage responses. Thanks to the utilization of the multiple-input MOS transistor technique, one differential pair with an arbitrary number of inputs is required for constructing the FDDA. Therefore, unlike the previously published FDDA-based universal filters, the proposed filter has the simplest CMOS structure with less power consumption than those already published in the literature. The filter operates with 0.5 V, consumes 740 nW and exhibits rail-to-rail input common mode range. The dynamic range of the BP filter is 73 dB for 1% third intermodulation distortion. The circuit was designed in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process design kit, and the simulation results confirm the advantages of the proposed filter.
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Multiple-Input Bulk-Driven MOS Transistor for Low-Voltage Low-Frequency Applications
(2019-06-15)
Khateb, Fabian
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Kulej, Tomasz
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Kumngern, Montree
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Psychalinos, Costas
This brief presents the principle and the first experimental results of the multiple-input bulk-driven (MIBD) MOS transistor (MOST) suitable for extremely low-voltage low-power integrated circuits. The MIBD MOST offers significant reduction in circuit complexity, power consumption and extension of the input common-mode range (ICMR). To confirm the benefits of the MIBD MOST, a differential difference amplifier (DDA) with very simple CMOS topology has been designed and fabricated in a standard n-well 0.18 µm CMOS process from TSMC with total chip area 226 µm × 78 µm. The DDA is supplied with 0.5 V and consumed only 1.23 µW, while the ICMR is rail-to-rail. The measured open-loop dc gain is 62 dB, the gain bandwidth product is 56.4 kHz, and the total harmonic distortion is 0.2% @ 1 kHz for 400 mV peak-to-peak input sine wave.
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A compact power-efficient 0.5 V fully differential difference amplifier
(2019-06-01)
Khateb, Fabian
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Kulej, Tomasz
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Kumngern, Montree
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Psychalinos, Costas
This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.
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1 V Rectifier Based on Bulk-Driven Quasi-Floating-Gate Differential Difference Amplifiers
(2015-07-18)
Khateb, Fabian
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Vlassis, Spyridon
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Kumngern, Montree
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Psychalinos, Costas
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Kulej, Tomasz
This paper presents experimental results for a low-voltage (LV) low-power (LP) voltage rectifier realization, employing two differential difference amplifiers (DDA) as active elements.The proposed DDA is based on the recently presented technique named bulk-driven quasi-floating-gate that enables the circuit to work with 1 V power supply voltage, threshold-to-supply (Formula presented.) ratio and modulation index factor (Formula presented. equal to 70 and 90 %, respectively. The competitive features of the proposed structure compared with other state-of-the-art circuits are the capability for working under LV supply, with extended common mode voltage range and improved input transconductance. The proposed circuit was designed, simulated, and fabricated employing the Cadence platform and MOS transistors models provided by the 0.35 μm CMOS AMIS process. The total chip area was 213 × 266 μ<sup>m2</sup>. The provided simulation and experimental results prove the attractive performances of the proposed rectifier topology.
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Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor
(2015-07-01)
Khateb, Fabian
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Lahiri, Abhirup
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Psychalinos, Costas
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Kumngern, Montree
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Kulej, Tomasz
A digitally programmable low-voltage highly linear transconductor (G<inf>m</inf> stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of ±0.5 V and consumes 36 μW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35 μm CMOS AMIS process with total chip area 213 μm × 266 μm. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.
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Sub-volt fully balanced differential difference amplifier
(2015-01-01)
Khateb, Fabian
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Kumngern, Montree
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Vlassis, Spyridon
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Psychalinos, Costas
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Kulej, Tomasz
This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.
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Differential difference current conveyor using bulk-driven technique for ultra-low-voltage applications
(2014-01-01)
Khateb, Fabian
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Kumngern, Montree
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Spyridon, Vlassis
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Psychalinos, Costas
Nowadays the necessity of having low-voltage operation and low-power consumption is essential for electronic devices, particularly for portable electronics. Therefore, this paper presents a new ultra-low-voltage CMOS topology for a differential difference current conveyor (DDCC) based on the bulk-driven (BD) principle. Due to the use of the BD technique, the proposed circuit is capable of working with a low supply voltage of ±0.3 V and consumes about 18.6 μW with a wide input common-mode range. The proposed BD-DDCC is suitable for ultra-low-voltage low-power applications. As application examples, a voltage-mode multifunction biquadratic filter based on two BD-DDCCs and four grounded passive elements, and a fourth-order band-pass filter are presented. All passive elements of both applications are grounded, which is advantageous for monolithic integration. Also, the input voltage signals are applied directly to the high input impedance terminals, which is a desirable feature for voltage-mode operation. The simulations were performed with PSPICE using the TSMC 0.18 μm n-well CMOS technology to prove the functionality and attractive results of the proposed circuit. © 2013 Springer Science+Business Media New York.

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