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New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation
(2023-01-01)
Kumar, Prashant
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Srivastava, Pushkar
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Ranjan, Rajeev Kumar
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Kumngern, Montree
We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., ∼ 67% improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx 1154.69 μ m2 and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.
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0.5 v Multiple-Input Multiple-Output Differential Difference Transconductance Amplifier and Its Applications to Shadow Filter and Oscillator
(2023-01-01)
Khateb, Fabian
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Kumngern, Montree
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Kulej, Tomasz
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Ranjan, Rajeev Kumar
This paper presents new applications of low-voltage and low-power multiple-input multiple-output differential difference transconductance amplifier (DDTA). The multiple-input bulk-driven MOS transistor (MIBD MOST) technique provides multiple-input of the active device that simplifies the application's topology and reduces its power consumption. The proposed DDTA has been used to realize multiple-input single-output shadow filter. Both voltage-and transimpedance-mode filtering functions can be obtained. The natural frequency and the quality factor of the shadow filter can be independently and electronically controlled using DDTA-based amplifiers. The proposed shadow filter has been modified to work as a shadow oscillator. The condition and frequency of oscillation can be controlled independently and electronically. The DDTA is capable to work with 0.5V supply voltage and consumes 218.2 nW. The applications have been designed and simulated in Cadence using $0.18\mu \text{m}$ TSMC CMOS technology.
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A compact floating and grounded memristor model using single active element
(2022-12-01)
Prasad, Sagar Surendra
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Kumar, Prashant
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Raj, Niranjan
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Sharma, Pankaj Kumar
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Priyadarshini, Bindu
Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.
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Mem-Elements Emulator Design with Experimental Validation and Its Application
(2021-01-01)
Raj, Niranjan
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Ranjan, Rajeev Kumar
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Khateb, Fabian
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Kumngern, Montree
An emulator circuit of Memristor, Memcapacitor, and Meminductor commonly termed as mem-elements has been demonstrated in this article. The circuit has been realized using the technique of current mode, which provides better performance over voltage mode counterparts. The current mode analog building blocks, along with a few passive components, have been used in the presented circuit implementation. The fingerprint characteristics have been observed in both simulation and experimental results, validating the theoretical analysis. The robustness of the presented design has been supported by performing different types of analysis like process corner, temperature, and non-volatility behavior. The mem-elements emulator design has been simulated using $0.18~\mu \text{m}$ TSMC process parameter, and ±1.2 V power supply has been used. The commercial ICs AD844 and CA3080 are used for the experimental demonstration of the proposed mem-elements design by making a prototype on a breadboard. A layout area of $4829~\mu \text{m}^{2}$ , $8098~\mu \text{m}^{2}$ , and $8061~\mu \text{m}^{2}$ respectively is required for the Memristor, Memcapacitor, and meminductor circuit. The power consumed by the mem-elements circuit is also provided. A chaotic has been implemented using mem-elements to show the usefulness of the emulator design.
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Charged controlled MEM-element emulator and its application in a chaotic system
(2020-01-01)
Sharma, Pankaj Kumar
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Ranjan, Rajeev Kumar
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Khateb, Fabian
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Kumngern, Montree
This article proposes a charged controlled emulator model for memristor and memcapacitor using second-generation Current Conveyor (CCIIs) and Analog Multiplier (AM). The grounded and floating mem-element circuits have been designed using two CCIIs and one multiplier in addition to some passive components. The grounded type of design requires three resistors and three capacitors while floating design necessitates only two resistors and two capacitors. With the help of a switch, the proposed design can be easily switched into a memristor or memcapacitor. The proposed emulator model has been theoretically analyzed and simulated in PSpice to substantiate the effectiveness and accuracy. The practicability of the circuit has been established using commercially available ICs AD844AN and AD633JN. Non-linear characteristics of the proposed memristor emulator have been used to design a chaotic system.
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0.5 V fully differential universal filter based on multiple input OTAs
(2020-01-01)
Jaikla, Winai
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Khateb, Fabian
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Kumngern, Montree
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Kulej, Tomasz
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Ranjan, Rajeev Kumar
The design of a low-power, low-voltage, fully-differential universal biquad filter is presented in this work, which is constructed from four multiple-input gate-driven operational transconductance amplifiers (MI-OTAs) along with one passive resistor and two passive capacitors. The scheme of presented biquad filter has three high-input impedance voltage nodes and single output voltage node. Five unity gain filtering functions, all-pass (AP), low-pass (LP), band-pass (BP), high-pass (HP) and band-stop (BS) responses, are obtained. The selection of output filtering responses is obtained without the need of component matching condition, inverting or double input voltage. With this feature, it can be easily controlled with digital programming. The quality factor (Q) and angular frequency (ω<inf>0</inf>) are electronically and independently tuned. Moreover, the adjustment of ω<inf>0</inf> and Q can be done without affecting the voltage gain. A workability of the design is confirmed via Cadence software and the Spectre simulator based on the 180 nm TSMC CMOS technology parameters. The proposed fully differential filter operates with 0.5 V supply voltage. The results verify that the proposed filter dissipates the total power of 53.3 nW. Additionally, the dynamic range (DR) of band-pass filtering function is 63 dB for 2% third intermodulation distortion (IMD). Also, the simulated RMS value of the band-pass filtering noise is 45 µV.
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Comparative performance study of multiple-input bulk-driven and multiple-input bulk-driven quasi-floating-gate DDCCs
(2019-08-01)
Khateb, Fabian
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Kulej, Tomasz
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Kumngern, Montree
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Jaikla, Winai
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Ranjan, Rajeev Kumar
This brief presents a comparative performance study of two recently presented techniques, the multiple-input bulk-driven (MI-BD) and the multiple-input bulk-driven quasi-floating-gate (MI-BD-QFG) MOS transistors (MOST). These techniques offer simplified CMOS structures of specific active elements and ensure near rail-to-rail operation capability under extremely low-voltage supply and reduced power consumption. However, to clarify the pros and cons of each technique, two Differential Difference Current Conveyors (DDCC) using MI-BD and MI-BD-QFG are compared. For the purpose of comparison, theoretical analysis such as small-signal model, open-loop gain, terminal resistances, gain bandwidth product, input referred thermal noise and maximum input range of the DDCCs are included. Furthermore, in order to provide a fair performance comparison both of the DDCCs is supplied with 0.4 V and consume same power 140 nW. The DDCCs were fabricated in a standard n-well 0.18 µm CMOS process from TSMC and hence the results are confirmed theoretically and experimentally.

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