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Author: search.filters.author.Thanachayanont, ApinuntSubject: search.filters.subject.Limiting amplifier

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    A 1.3-V, 9.1μW wide-dynamic range logarithmic amplifier for cochlear implant system
    (2014-01-01)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a low-noise, low-power, wide-dynamic-range CMOS logarithmic amplifier for cochlear implant system in a standard 0.18μm CMOS technology. The proposed logarithmic amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. The overall circuit consumes only 9.1 μW from a 1.3 V single power supply voltage. The simulated input dynamic range is 80 dB, which covers the input amplitudes ranging from 10 μV to 100 mV. The simulated bandwidth of the amplifier is from 50 Hz to 24 kHz. The simulated total input-referred noise is 4.81 μV, integrated from 100 Hz to 10 kHz. © 2014 IEEE.
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    A 0.7-V, 2.86-μW low-noise logarithmic amplifier for neural recording system
    (2013-12-01)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper describes the design and realization of a low-noise, low-voltage, low-power CMOS logarithmic amplifier for bio-signal and neural recording applications. The proposed logarithmic amplifier is based on the progressive-compression parallel-summation architecture with DC offset cancellation feedback loop. A new fully differential limiting amplifier with bulk-driven current mirror active load is proposed to achieve larger voltage gain and low voltage operation. The proposed logarithmic amplifier was designed and simulated with process parameters from a standard 0.18-μm CMOS technology. The circuit operates with a single 0.7-V power supply voltage and dissipates 2.86 μW. The simulated input dynamic range is about 60 dB, which covers the input amplitudes ranging from 10 μV to 10 mV. The simulated -3-dB bandwidth of the amplifier is from 0.32 Hz to 22 kHz. The simulated total input-referred noise, integrated from 0.1 Hz to 10 kHz, is 4.41 μV. © 2013 IEEE.
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    A low-power CMOS RF power detector
    (2012-12-01)
    Sakphrom, Siraporn
    ;
    Thanachayanont, Apinunt
    This paper describes the design and implementation of a low-power wide dynamic range radio-frequency (RF) power detector in a standard 0.18-μm CMOS process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier. The RMS power detector exploits the nonlinear characteristic of MOSFET to realize the RMS conversion. A current-mirror active load is used in the RMS power detector to increase the RMS conversion gain. Since the output of the RMS power detector is a DC voltage, the following logarithmic amplifier does not require wide operating bandwidth, thus allowing simple circuit realization with minimum power dissipation. Simple differential amplifier is used to realize the limiting gain stage. Post-layout simulation results showed that the proposed circuit was able to detect input power from -70 dBm to -20 dBm with signal frequencies ranging from 0.5 GHz to 5 GHz, while dissipating only 0.9 mW under a 1.8-V power supply voltage. © 2012 IEEE.