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Author: search.filters.author.Wisayataksin, SumekSubject: search.filters.subject.FPGA

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    Configurable Hardware Architecture of Multidimensional Convolution Coprocessor
    (2021-01-20)
    Boonyuu, Geranun
    ;
    Wisayataksin, Sumek
    We propose a configurable coprocessor for the convolutional neural network (CNN) that suit various models of CNN. It can operate 2D standard convolution, 2D depthwise separable convolution, 3D convolution, and a fully connected layer. The proposed processing cluster consists of 72 processing units (PUs) of half-precision floating-point to assist the main processor in embedded systems. The experimental results on Artix-7 FPGA revealed that our design has 12.16 GOPs per cluster. Moreover, this architecture was designed to be scalable for the systems with higher performance.
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    An efficient hardware architecture of Codec2 low bit-rate speech decoder
    (2019-07-01)
    Wisayataksin, Sumek
    Speech coding algorithms have been developed for years to digitalize human voice to a few binary bits as possible while maintaining reasonable quality. Codec2 vocoder algorithm is one of an efficient sinusoidal coding with very high compression rate down to 450 bit/s. In this paper, an efficient hardware architecture of Codec2 decoder is proposed to increase the performance of voice decoding process and reduce comprehensive tasks from a host processor. Although the sinusoidal decoding algorithm is complicated with many arithmetic operations such as the arithmetic of complex numbers, FFT, FIR filter, division, trigonometry, exponential and logarithm functions, several techniques were explored to optimize and parallelize a datapath of the proposed hardware. The implementation on Xilinx Artix-7 FPGA revealed that the proposed architecture could reduce the processing time up to 20 times, compared to the conventional Cortex-M4 CPU running with the original software.
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    A programmable artificial neural network coprocessor for handwritten digit recognition
    (2019-07-01)
    Wisayataksin, Sumek
    ;
    Boonyuu, Geranun
    This paper proposes the hardware architecture of an artificial neural network coprocessor that its structure can be programmable. The number of neurons in each layer of a feedforward network can be set by writing configuration registers. The processing unit with four MACs and the sigmoid calculation engine are connected in eight pipeline stages to enhance the processing speed. The application of handwritten digit recognition from the MNIST database was performed to verify the performance of proposed architecture. The design was developed with Verilog HDL and implemented on the Xilinx Artix-7 XC7A35T FPGA. The experimental results revealed that the speed of back-propagation learning and validation process can be up to 47 times faster than computation on ARM Cortex-A4 CPU, while the recognition rate is still the same.