KMITL

Permanent URI for this communityhttps://dspace.kmitl.ac.th/handle/123456789/1

Browse

Settings

Subject: search.filters.subject.biomedical applications

Search Results

Now showing 1 - 3 of 3
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications
    (2018-06-30)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18μm CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027mm<sup>2</sup>. The overall circuit consumes 9.75μW from a single 1.5V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80dB input dynamic range (from 10μV to 100mV), a bandwidth of 4Hz-10kHz, and a total input-referred noise of 5.52μV.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications
    (2016-01-01)
    Sundarasaradula, Yuwadee
    ;
    Constandinou, Timothy G.
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    A 1-V, 6-nW programmable 4th-order bandpass filter for biomedical applications
    (2015-08-06)
    Sundarasaradula, Yuwadee
    ;
    Thanachayanont, Apinunt
    This paper presents the design and realization of a programmable 4<sup>th</sup>-order bandpass filter for biomedical applications in a standard 0.18 μm CMOS technology. The center frequency is adjustable from 80 Hz to 7 KHz, using a 6-bit digital-to-analog-converter (DAC). At a center frequency of 1 KHz and quality factor of 4, the simulated dynamic range is 53.6 dB for 1% total harmonic distortion (THD) and the simulated total input-referred noise, integrated from 875 Hz to 1.125 KHz, is 177μV. The filter consumes only 6 nW from a 1-V single power supply voltage.