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Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications.
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Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures
(2025-01-01)
Sato, Tomoaki
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Murakami, Anyu
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Chivapreecha, Sorawat
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Moungnoul, Phichet
RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4.
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Optimal Number of Wires for Circuits on RTLDesigned FPGAs
(2024-01-01)
Sato, Tomoaki
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Hayashihara, Yuya
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Yokota, Shione
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Chivapreecha, Sorawat
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Moungnoul, Phichet
FPGAs (Field-Programmable Gate Arrays) with reconfigurable features are used in various applications. However, circuits on FPGAs are inferior to circuits on ASICs in operating frequency, power consumption, and area. Co-design of FPGA and ASIC is one way to solve this problem. To realize this co-design, RTL-Designed FPGAs have been proposed by the authors. The features of the FPGAs are that they can be described only with HDL and that they can be realized with ordinary standard cells. Therefore, FPGAs and ASICs can be co-designed easily. Until now, the FPGAs have not been considered for optimal wiring count. In this paper, we clarify the optimum number of wires using a 4-bit adder circuit. In addition, cases in which more than that optimal number of wires is needed are discussed.
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Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
(2018-12-24)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Higuchi, Kohji
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Moungnoul, Phichet
Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAS, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAS, fine-Tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
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Throughput of a Firewall Unit on FPGAS Developed by the RTL Design Methodology
(2017-10-19)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Moungnoul, Phichet
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Higuchi, Kohji
The transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAS (field-programmable gate arrays) which are developed by the RTL (register-Transfer level) design methodology. As an application of the FPGAS for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.
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An FPGA architecture for ASIC-FPGA co-design to streamline processing of IDSs
(2016-01-01)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Moungnoul, Phichet
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Higuchi, Kohji
Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a field-programmable gate array (FPGA) can apply to cyber security processing on mobile devices. By using the FPGA, cyber security processing is able to use parallel processing, super pipeline and processing that is independent of a word width size. However, the FPGA has a problem that the delay times of arithmetic circuits are longer than that of an application specific integrated circuit (ASIC) or CPU. In this paper, the authors propose an FPGA architecture for ASIC-FPGA co-design for addressing the problem. In order to evaluate the architecture, adders are enhanced by ASIC-FPGA co-design and evaluated. As a result, it is shown that the problem with the delay times of arithmetic circuits is solved.
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A crossbar switch circuit design for reconfigurable wave-pipelined circuits
(2014-01-01)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Moungnoul, Phichet
This paper states crossbar switches which are used for the efficient design in reconfigurable wave-pipelined circuits. In the hardware- and host-based IPS (Intrusion Prevention System) which is used in mobile computing, reconfigurable circuits for intrusion detecting are implemented and their design requires techniques for highspeed and low-power operations. Wave-pipeline is a technique for realizing them. On the other hand, using it makes a problem that consumes a large amount of logic block in a conventional FPGA (Field-Programmable Gate Array). To solve this problem, the authors have developed a logic block for wave-pipelining. However, a crossbar switch for controlling the logic blocks to be used has not been developed. In this paper, the crossbar switches are developed in RTL (Register Transfer Level) and delay times, area and power are calculated.
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A logic block for wave-pipelining
(2013-12-01)
Sato, Tomoaki
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Chivapreecha, Sorawat
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Moungnoul, Phichet
An FPGA (Field-Programmable Gate Array) device is selected in order to shorten the development life cycle of a processor. Using the FPGA is disadvantageous than using custom LSI (Large-Scale Integrated circuit) in terms of power consumption and operating frequency. That is, circuit design in the FPGA is required to design methods for high-speed and low-power operations. Wave-pipeline is one of a circuit design technique for high-speed processing and low power consumption. However, the design method has the problem of consuming a large number of logic blocks. To solve this problem, a logic block for wave-pipelining is proposed. The logic block is developed using 0.18-micron C-MOS (Complementary Metal-Oxide-Semiconductor) technology. A wave-pipelined adder which is made with the logic blocks is evaluated in the chip area. As a result, it is shown that the area of the adder which use the logic blocks is less than that of the adder without the logic blocks.
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Development of a WiMAX processor by using a CPLD
(2010-12-01)
Sato, Tomoaki
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Moungnoul, Phichet
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Fukase, Masa Aki
WiMAX (Worldwide Interoperability for Microwave Access) is one of the standards for high-speed wireless communications. The development cycle of a WiMAX processor is short because a transmission rate of a WiMAX system improves gradually. To keep using it even when the speed improves, there is a method of development that uses a processor that can be a reconfiguration of a circuits. In this paper, a mobile WiMAX processor by using a CPLD (Complex Programmable Logic Device) is proposed. Because wave-pipeline technique is used, the problem of processing speed is canceled. The authors evaluate wave-pipelined circuits which WiMAX processor needs on a CPLD. It is made clear that wave-pipeline technique is effective in the circuits on the CPLD.

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