A logic block for wave-pipelining

An FPGA (Field-Programmable Gate Array) device is selected in order to shorten the development life cycle of a processor. Using the FPGA is disadvantageous than using custom LSI (Large-Scale Integrated circuit) in terms of power consumption and operating frequency. That is, circuit design in the FPGA is required to design methods for high-speed and low-power operations. Wave-pipeline is one of a circuit design technique for high-speed processing and low power consumption. However, the design method has the problem of consuming a large number of logic blocks. To solve this problem, a logic block for wave-pipelining is proposed. The logic block is developed using 0.18-micron C-MOS (Complementary Metal-Oxide-Semiconductor) technology. A wave-pipelined adder which is made with the logic blocks is evaluated in the chip area. As a result, it is shown that the area of the adder which use the logic blocks is less than that of the adder without the logic blocks.