Search Results

Now showing 1 - 7 of 7

Some of the metrics are blocked by your
consent settings
0.3-V Nanopower Biopotential Low-Pass Filter
(2020-01-01)
Kulej, Tomasz
;
Khateb, Fabian
;
Kumngern, Montree
This paper presents a compact power-efficient CMOS fourth-order low-pass filter suitable for electrocardiogram (ECG) acquisition systems. The CMOS structure of the proposed filter utilize the bulk-driven technique and operates in subthreshold region to achieve extremely low-voltage supply (0.3V) and nanopower consumption (0.676 nW) for cut-off frequency of 100 Hz. The filter was designed and simulated using 0.18μm CMOS TSMC technology. The total input referred noise of the filter is 87μ Vrms and the dynamic range is 58.1 dB. The filter offers the best figure of merit of 2.91× 10-14 J, the lowest power consumption and voltage supply, compared with the previous state-of-the-art nanowatt filter designs.
Some of the metrics are blocked by your
consent settings
1V High speed E-TSPC 2/3 prescalers
(2019-07-01)
Lawang, Itthiphat
;
Tudsorn, Apirak
;
Tooprakai, Siraphop
This paper presents a 1V High Speed E-TSPC 2/3 Prescalers. The true single-phase clock divider was developed to constitute work faster and low power. All simulation results are performed using the Hspice simulator program. And uesd CMOS technology on 45 mm. The power consumption of the proposed circuit will consume less power than other circuits previously. The maximum input frequency for simulations of the suggested prescaler reaches up to 24GHz at 1V supply voltage.
Some of the metrics are blocked by your
consent settings
Design of a low-power wide dynamic range CMOS RF power detector
(2015-10-02)
Thanachayanont, A.
This article describes the design and implementation of a low-power wide dynamic range radio-frequency power detector in a standard 0.18-µm complementary metal-oxide-semiconductor process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier. The RMS power detector exploits the non-linear characteristic of metal-oxide-semiconductor field-effect transistor to realise the RMS conversion. Since the output of the RMS power detector is a DC voltage, the following logarithmic amplifier does not require wide operating bandwidth, thus allowing simple circuit realisation with minimum power dissipation. Simple differential amplifier is used to realise the limiting gain stage. Post-layout simulation results showed that the proposed circuit was able to detect input power from −70 dBm to −20 dBm, with signal frequencies ranging from 0.5 GHz to 3.0 GHz, while dissipating 0.9 mW under a 1.8-V power supply voltage.
Some of the metrics are blocked by your
consent settings
A 1.2 v low-power true single-phase clock CMOS 2/3 prescalers
(2014-11-05)
Tooprakai, Siraphop
;
Tudsorn, Apirak
This paper presents a low-power true single-phase clock 2/3 prescalers at 1.2 V supply voltage. The true single-phase clock divider was developed to help achieve low power and highspeed. All simulation results have been carried out by using Hspice program simulator based on 0.13μm CMOS technology. The power consumption of the proposed circuit is less than that of the previous circuits. The prescaler is capable of operating from 0.5 to 9.7 GHz.
Some of the metrics are blocked by your
consent settings
A 0.5 V quasi-floating gate self-cascode DTMOS current-mode precision full-wave rectifier
(2012-10-02)
Mitwong, Hanphon
;
Kasemsuwan, Varakorn
This paper presents a 0.5 V quasi-floating gate self-cascode DTMOS current-mode precision full-wave rectifiers (PFWR). The circuit is designed based on improved Wilson current mirrors. All MOS transistors are biased on the edge of conduction, enabling the circuit to operate at low voltage with low power consumption. Negative feedback mechanism of the Wilson current mirror and cross coupling techniques have been employed to reduce the input impedance. Spectre is used to perform the simulation and the results show the frequency of operation as high as 100 MHz using a standard 0.13 μm CMOS technology. The mismatch between the input and rectifier's output is 0.24% for an input current of ±100 μA. The DC transfer characteristic shows good linearity, very sharp corner at zero crossing point and good symmetry during positive and negative input cycle, while power dissipation is 570 nW © 2012 IEEE.
Some of the metrics are blocked by your
consent settings
A low-voltage low-power current-mode differential adjustable Schmitt trigger
(2012-10-02)
Tamnupan, Wuttipong
;
Kasemsuwan, Varakorn
This paper presents a low-voltage low-power current-mode differential adjustable Schmitt trigger. The proposed Schmitt trigger consists of current subtractor, current Schmitt trigger and voltage to current converter. The operation range is extended to all four quadrants of the input-output plane. Schmitt trigger is designed using UMC 0.13 μm CMOS technology and operates under the supply voltage of 0.7 V. The simulation results show that the hysteresis lie in the all quadrant of the input-output plane and the power dissipation is only 66 μW. © 2012 IEEE.
Some of the metrics are blocked by your
consent settings
A 0.6 volt class-AB CMOS voltage follower with bulk-driven quasi-floating gate super source follower
(2012-10-02)
Wangtaphan, Skawrat
;
Kasemsuwan, Varakorn
This paper presents a design of 0.6 V class-AB voltage follower (VF) using 0.13 μm CMOS technology. The follower is developed based on the super source follower (SSF) using bulk-driven and quasi-floating gate (QFG) techniques. The proposed VF can operate at low voltage without DC level shift between the input and output terminals. The simulation results show the total harmonic of 0.3 % for an input/output voltage of 0.18 V <inf>pp</inf> at 100 kHz (R <inf>L</inf>//C <inf>L</inf>=5 kΩ//100 pF). The power dissipation is found to be 38 μW. © 2012 IEEE.

KMITL

Browse

Filters

Settings

Sort By

Results per page

Search Results