Design of a low-power wide dynamic range CMOS RF power detector

This article describes the design and implementation of a low-power wide dynamic range radio-frequency power detector in a standard 0.18-µm complementary metal-oxide-semiconductor process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier. The RMS power detector exploits the non-linear characteristic of metal-oxide-semiconductor field-effect transistor to realise the RMS conversion. Since the output of the RMS power detector is a DC voltage, the following logarithmic amplifier does not require wide operating bandwidth, thus allowing simple circuit realisation with minimum power dissipation. Simple differential amplifier is used to realise the limiting gain stage. Post-layout simulation results showed that the proposed circuit was able to detect input power from −70 dBm to −20 dBm, with signal frequencies ranging from 0.5 GHz to 3.0 GHz, while dissipating 0.9 mW under a 1.8-V power supply voltage.