Tooprakai, Sirapop

Preferred name

Tooprakai, Sirapop

Alternative Name

Tooprakai, Siraphop

Main Affiliation

School of Engineering

Email

sirapop.to@kmitl.ac.th

Now showing 1 - 1 of 1

Some of the metrics are blocked by your
consent settings
Multi-input Memristor Rationed Logic Full Adder Circuit for Efficient Processing Time
(2022-01-01)
Yamtim, Suparlerk
;
Tooprakai, Siraphop
This research proposes a multi-input memristor rationed logic (MRL) 1-bit full adder circuit as an alternative to conventional multi-stage MRL full adders. The proposed multi-input 1-bit full adder circuit consisted of 25 memristors without CMOS transistor. Ripple carry adder was utilized to realize multi-input MRL 8-bit full adder circuit by cascading eight blocks of multi-input MRL 1-bit full adder. The advantages of the multi-input MRL 8-bit full adder include straightforwardness, compactness, and improved delay time. Simulations were carried out by using LTspice simulator and results compared with multi-stage full adders. The multi-input MRL 8-bit full adder circuit achieved higher processing-time efficiency and thereby holds great potential as an alternative to multi-stage full adders. The novelty of this research lies in the use of multi-input MRL technique to realize full adder circuits that effectively mitigate voltage degradation and improve delay time.