Tooprakai, Sirapop

Preferred name

Tooprakai, Sirapop

Alternative Name

Tooprakai, Siraphop

Main Affiliation

School of Engineering

sirapop.to@kmitl.ac.th

Now showing 1 - 10 of 22

Some of the metrics are blocked by your
consent settings
An electrostatic discharge free bootstrapped BiCMOS inverter circuit based on parasitic diode
(2008-12-01)
Tooprakai, Siraphop
;
Dejhan, Kobchai
Electrostatic discharge (ESD) free bootstrapped BiCMOS inverter circuit is proposed. The proposed driver circuit uses the bootstrapped technique; the transistor base voltage is higher than the supply voltage. The input of circuit is arranged to protect the electrostatic discharge problem, and the output waveform is able to have full swing. The proposed circuit consumes low power with small delay time. The transistors in the circuit operate with high performance and efficiency. © 2008 World Scientific Publishing Company.
Some of the metrics are blocked by your
consent settings
Current-Mode Active Filter Using EX-CCCII
(2024-06-01)
Kumngern, Montree
;
Khateb, Fabian
;
Kulej, Tomasz
;
Tooprakai, Siraphop
This paper presents a novel multiple-input and multiple-output current-mode universal analog filter with electronic tuning capability. The proposed circuit uses a single second-generation current-controlled current conveyor with extra-X terminals (EX-CCCII) and two grounded capacitors. The filter can offer five standard filtering functions, namely low-pass, high-pass, band-pass, band-stop, all-pass responses, in the same circuit without changing the internal configuration of the filter by selecting appropriate input and output signals. To obtain the five standard filtering functions, inverted input signal and input matching conditions are absent. The natural frequency of all filter responses can be electronically controlled. The proposed circuit was simulated by SPICE using 0.18 μm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC). The results of experiments using the integrated circuit operational amplifier AD844 confirm the functionality of the new filter.
Some of the metrics are blocked by your
consent settings
Efficient Processing Time with Carry-lookahead Adder Memristor Rationed Logic
(2023-01-01)
Yamtim, Suparlerk
;
Tooprakai, Siraphop
This paper presents a novel approach to the design of full adder circuits, leveraging the unique properties of memristors and CMOS logic in a hybrid system. This paper explores the design and operation of memristor-based logic gates, including AND, OR, NAND, and NOR gates, realized through CMOS inverters. This paper further proposes a full adder circuit using Hybrid Memristor-CMOS logic and a carry look-Ahead adder (CLA). Our simulations demonstrate that the proposed full adder circuit outperforms traditional RCA-based circuits in terms of speed. This work contributes to the ongoing discourse in digital electronics, offering fresh perspectives and potential solutions to existing challenges, and hope it will inspire further research in the field of memristor-based digital electronics.
Some of the metrics are blocked by your
consent settings
Multi-input Memristor Rationed Logic Full Adder Circuit for Efficient Processing Time
(2022-01-01)
Yamtim, Suparlerk
;
Tooprakai, Siraphop
This research proposes a multi-input memristor rationed logic (MRL) 1-bit full adder circuit as an alternative to conventional multi-stage MRL full adders. The proposed multi-input 1-bit full adder circuit consisted of 25 memristors without CMOS transistor. Ripple carry adder was utilized to realize multi-input MRL 8-bit full adder circuit by cascading eight blocks of multi-input MRL 1-bit full adder. The advantages of the multi-input MRL 8-bit full adder include straightforwardness, compactness, and improved delay time. Simulations were carried out by using LTspice simulator and results compared with multi-stage full adders. The multi-input MRL 8-bit full adder circuit achieved higher processing-time efficiency and thereby holds great potential as an alternative to multi-stage full adders. The novelty of this research lies in the use of multi-input MRL technique to realize full adder circuits that effectively mitigate voltage degradation and improve delay time.
Some of the metrics are blocked by your
consent settings
A 1.2 v low-power true single-phase clock CMOS 2/3 prescalers
(2014-11-05)
Tooprakai, Siraphop
;
Tudsorn, Apirak
This paper presents a low-power true single-phase clock 2/3 prescalers at 1.2 V supply voltage. The true single-phase clock divider was developed to help achieve low power and highspeed. All simulation results have been carried out by using Hspice program simulator based on 0.13μm CMOS technology. The power consumption of the proposed circuit is less than that of the previous circuits. The prescaler is capable of operating from 0.5 to 9.7 GHz.
Some of the metrics are blocked by your
consent settings
Path loss comparison in 850 MHz and 1800 MHz frequency bands
(2016-09-06)
Bhupuak, Wiyada
;
Tooprakai, Siraphop
Nowadays people widely used mobile phone instead of using landlines phones. This paper proposes to compare the path loss in 850 MHz and 1800 MHz frequency bands by various path loss models. The path loss under terms of the transmitter height and the receiver height. The well known path loss model such as Walfisch-Ikegami (WI), SUI and Ericsson model used to simulate path loss by MATLAB. The results shown that when the longest distance WI model has the most path loss at the receiving antenna height is 1 and 5 meters. The path loss in the frequency bands 1800 MHz is greater than the path loss in the frequency bands 850 MHz under the same conditions. The path loss can be use to determine where to install the mobile base station with high quality. That means at the same distance if using the frequency band 1800 MHz for mobile network in the same technology will require to install the mobiles base station more than using frequency band 800 MHz.
Some of the metrics are blocked by your
consent settings
1V High speed E-TSPC 2/3 prescalers
(2019-07-01)
Lawang, Itthiphat
;
Tudsorn, Apirak
;
Tooprakai, Siraphop
This paper presents a 1V High Speed E-TSPC 2/3 Prescalers. The true single-phase clock divider was developed to constitute work faster and low power. All simulation results are performed using the Hspice simulator program. And uesd CMOS technology on 45 mm. The power consumption of the proposed circuit will consume less power than other circuits previously. The maximum input frequency for simulations of the suggested prescaler reaches up to 24GHz at 1V supply voltage.
Some of the metrics are blocked by your
consent settings
Estimation of Protection Distance between Digital TV Signals in Adjacent Channel on Terrestrial Television
(2025-01-01)
Chomsuk, Kinupong
;
Tooprakai, Siraphop
The Office of the National Broadcasting and Telecommunication Commission (NBTC) of Thailand initiated the transition to digital broadcasting. The implementation process requires a broadcasting license and digital transmission testing, which was carried out on channel 29 and channel 30 - adjacent channels. Due to the 20 MHz spacing between these signals, adjacent channel interference is inevitable. This study experimentally evaluates the degradation caused by interference between digital television signals operating on adjacent channels in terrestrial television broadcasting.A novel aspect of this research is the use of field strength measurements to assess the impact of adjacent channel interference on digital TV signals within urban areas. The results demonstrate that most measured protection ratios (PR) align with the ITU-R recommended value of -11 dB. This confirms that the power ratio is affected by spectrum overlap rather than the distance from the trasmitter station.
Some of the metrics are blocked by your
consent settings
Design high speed and low power hybrid full adder circuit
(2018-12-24)
Lueangsongchai, Sathaporn
;
Tooprakai, Siraphop
This paper presents 1-bit hybrid full adder cells circuit scheme that high speed and low power consumption. This Full adder cells circuit is designed utilization of XOR gate, XNOR gate, pass logic gate and transmission gate. Result of simulation by HSPICE program based on 16 nm CMOS technology with 0.9V power supply voltage and maximum frequency at 8GHz.
Some of the metrics are blocked by your
consent settings
Maintenance Decision Modeling for Solar Photovoltaic Performance Prediction Using RMSE and MAPE Methods
(2025-01-01)
Aree, Sompong
;
Tooprakai, Siraphop
This study evaluates the efficiency and degradation of a 999.50 kWp photovoltaic (PV) system in Thailand under clear sky conditions. It found that the system efficiency ratio significantly decreased, 10% below the design threshold. Thus, a feasible and optimal model can be identified to support better maintenance decisions. In addition, a real-time performance monitoring approach is proposed to enable building operators to make informed decisions about mechanical maintenance or cleaning maintenance. This method involves comparing the actual power generation data with the efficiency prediction based on linear regression modeling. In addition, the impact of dirt accumulation on the efficiency of the PV modules is evaluated. The preliminary results indicate that the output power decreases to 213.74 kW, and the corresponding efficiency ratio is 46.76%. A linear regression-based warning mechanism is adopted to issue an alarm when the efficiency drops below a threshold of 50% ± 10 or when the power drops below 300 kW ± 50. The results show that using this prediction approach can improve the system efficiency ratio by up to 70% and increase the output power by more than 355.53 kW. The accuracy of the model is verified with a mean square error(RMSE) of 18.86% or more than 81.14% and a mean absolute percentage error(MAPE) of 4.56%. The study concludes that the prediction simulation can effectively guide maintenance interventions, which can improve both power generation and system efficiency. Future work may incorporate AI-driven predictive analysis to further optimize the PV system and maintenance strategies.

Tooprakai, Sirapop

Filters

Settings

Sort By

Results per page