Kongpoon, Metha
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Item type:Publication, A low-power and wide dynamic range class-AB Sinh differentiator(2013-12-01)Companding, current mode, class-AB, Sinh filters provide high dynamic range with only half the capacitor value needed compared to the pseudo class-AB log-domain filters counterpart. Most Sinh filters, however, arise from the basic Sinh integrator building block. This paper describes the synthesis of a new, companding, Class-AB Sinh current mode differentiator which offers a basic building block for the current mode filters with the advantage of 1/f noise suppression due to a low frequency attenuation of the differentiator. The proposed differentiator was designed and simulated with HSPICE program using 0.35μm AMS CMOS process. With power supply of ±1V and the operating frequency range of 1Hz-100kHz, the proposed differentiator exhibited simulated input dynamic range of 98dB at operating frequency of 1kHz, and the power consumption of 0.36μW-7.2μW. © 2013 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A Voltage Mode Fully Differential Implementation of Mihalas-Niebur Neuron with Biological-Timescale(2018-07-02); Leelavattananon, KritsaponThis paper presents an implementation of the Mihalas-Niebur neuron model using voltage mode differential \mathbf{g}-{\mathbf{m} {\pmb{-}}} C filter based on a multiple input transconductor. The transconductance linearization technique was employed to achieve the biologically realistic time constant. With the moderate value of the bias current and the small size capacitors, the proposed neuron can exhibit different spiking and bursting patterns on the biological timescale. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Multiplier-less and compact FPGA implementation of Mihalas-Niebur neuron(2019-11-01); Leelavattananon, KritsaponThe modified Mihalas-Niebur neuron model suitable for a compact digital implementation is presented. Based on the modified model, a multiplier-less and compact Mihalas-Niebur neuron that uses word-length optimization and bitwise shifting operators for the multiplication was designed and implemented on an FPGA. The simulation results show that the proposed neuron successfully produces all 20 prominent spiking patterns with a few FPGA resources used. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Ultra-low-power, modular, class-AB current multiplier(2019-07-01)This paper describes a modular class-AB current multiplier which provides the good linearity, the linearly tunable conversion gain and the robustness to process mismatch. The proposed multiplier is derived from a hyperbolic sine multiplication identity, and was designed and simulated using 0.35 μm AMS CMOS process. Simulation results show that the improved linearity, linearly tunable conversion gain and better process variation robustness can be achieved while utilizing lower power consumption and the slightly higher number of transistors compared to the state-of-the-art class-AB current multiplier. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, An instrumentation amplifier based on a floating gate fully differential CCII with DEO rejection for ECG acquisition systems(2014-01-01);