Sirimasakul, Silar

Loading...
Thumbnail Image
Preferred name
Sirimasakul, Silar
Alternative Name
Sirimasakul, S.
Main Affiliation
Email
silar.si@kmitl.ac.th

Settings

Now showing 1 - 3 of 3
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    A Logarithmic Level-Crossing ADC with Fixed Comparison Window
    (2022-01-01)
    Sirimasakul, Silar
    ;
    Thanachayanont, Apinunt
    This paper describes the design and realization of a logarithmic level-crossing analog-to-digital converter with fixed comparison window. The proposed circuit comprises two comparators, a logarithmic charge-sharing digital-to-analog converter, a control logic circuit, and an up/down counter. The circuit is designed and simulated with process parameters from a 0.18 μm CMOS technology and a 1.8 V power supply voltage. Simulation results showed that the overall circuit exhibited the minimum resolution of 3.9mV and the maximum INL and DNL errors of -0.17LSB and -0.09LSB, respectively.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    Ultra-low-power differential ISFET/REFET readout circuit
    (2009-01-01)
    Thanachayanont, Apinunt
    ;
    Sirimasakul, Silar
    A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage. © 2009 ETRI.
  • Loading...
    Thumbnail Image
    Some of the metrics are blocked by your 
    consent settings
    Item type:Publication,
    A logarithmic level-crossing ADC
    (2017-11-03)
    Sirimasakul, Silar
    ;
    Thanachayanont, Apinunt
    A 3-bit logarithmic level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Based on the feedback LC-ADC structure, the proposed circuit is realized by using logarithmic charge-scaling digital-to-analog converters. The circuit is designed and simulated with process parameters from a 0.35-μm CMOS technology and a 1.5-V power supply voltage. Process corner simulation results showed that the INL and DNL errors are within the range of +0.14/-0.09LSB and +0.14/-0.21LSB, respectively.