Pakasiri, Chatrpol

Preferred name

Pakasiri, Chatrpol

Alternative Name

Pakasiri, Charpol

Main Affiliation

Integrated Innovative Technology

chatrpol.pa@kmitl.ac.th

Now showing 1 - 10 of 26

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Impedance Extraction using Impedance Perturbation Method of Electrically Small HF Loop Antenna with Undercover Ferrite Sheet
(2018-12-24)
Mangmisirisap, Kanthiphat
;
Bandudej, Kamorn
;
Pakasiri, Chatrpol
Electrically small high frequency (HF) loop antenna with undercover ferrite sheet yields high radiation resistance for multi-Turn structure. Antenna impedance without radiation differs greatly from that with the radiation effect. Impedance perturbation method is used for extracting antenna impedance with radiation effect at a desired frequency. Matching networks are designed based on the extracted antenna impedance. The measurement results show that the antenna with the designed matching network provides higher return loss.
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A UHF compact complex impedance-transforming balun with high isolation
(2020-01-01)
Nithiporndecha, Kittipong
;
Pakasiri, Chatrpol
Background: A compact complex impedance-transforming balun for UHF frequencies, which is based on a coupled-line structure that matched all ports and provided high output port iso-lation, was designed in this paper. Methods: A lumped component transformation was used to minimize circuit size. The implemented circuit operated at 433 MHz with the reflection coefficients less than-16 dB at all ports, 0.22 dB amplitude balance and 180° phase balance at the output ports. The signal coupling between the output ports was-16.8 dB. The circuit size is small at 0.032λ. Results: Complex impedance-transforming baluns were designed to operate at 433 MHz. The source impedance at port 1 was set at Z<inf>s</inf> = 12-j12Ω and the load impedances at port 2 and 3 were set at Z<inf>L</inf> = 80 + j30Ω. Conclusion: A compact complex impedance-transforming balun at UHF frequency, with all ports matched and high isolations, was designed and illustrated in this paper.
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Modeling a Simple Single-phase Grid-connected Photovoltaic System Using Negative Conductance of Solar Cells
(2023-01-01)
Somdock, Nuttakrit
;
Pakasiri, Chatrpol
;
Sakulkalavek, Aparpron
;
Sirichote, Wichit
This paper presents the simulation of a simple single-phase grid-connected photovoltaic (PV) system using the PSPICE model. The modeling system consists of a PV string, a single-phase current source inverter (CSI), load, and a grid voltage source. The system uses the PV string as the current source. The single-phase CSI was controlled by the grid AC voltage. The operation of the system employs the negative conductance characteristics of the PV string. We studied the voltage and current waveform at the inverter output terminal, the current waveform at the load, the AC power with various open-circuit voltages and temperatures of the PV string. The result showed the current waveform at the inverter output terminal follows the I-V characteristics of the PV string. The current waveform at the load depends on its impedance characteristics. The AC power increased with the open circuit voltage. We found that the maximum efficiency of the AC power conversion system was 63.3% at the peak of the AC voltage source, which was equal to the maximum power voltage of the PV string. In addition, the prototype was built for testing and testing verified the simulation results. The experimental results showed the current waveform at the inverter terminal and load were similar to the simulation results.
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Simple Class F Power Amplifier Design with Fundamental Frequency Tuning
(2020-03-01)
Manasammakij, Prateep
;
Pongthavornkamol, Tiwat
;
Pakasiri, Chatrpol
Simple class F with medium output power at 433 MHz is designed and simulated in this paper. The design process uses fundamental frequency tuning in find the matching network. At fundamental frequency, the reactance part of the networks needs to be conjugate values of that of the output impedance of the transistor circuit while the resistance part of the network is found by running simulation sweep. The second and third harmonics are also considered in the matching network design. Using the designed matching networks, the amplifiers yield almost optimum efficiency values for input power of 13 and 18 dBm. The proposed technique can save computational costs comparing to load pull technique. In future work it can lead to implementation of a class F power amplifier without using load pull.
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Two CMOS Wilkinson Power Dividers Using High Slow-Wave and Low-Loss Transmission Lines
(2024-08-01)
Pakasiri, Chatrpol
;
Teng, Wei Sen
;
Wang, Sen
This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λ<inf>o</inf>2.
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Improvement of HF RFID reader performance under metallic environment using ferrite sheet
(2017-12-19)
Kankhunthod, Kittipon
;
Lekawat, Lertsak
;
Pakasiri, Charpol
Conventional loop antennas for RFID reader usually perform worse with metallic environment. To improve reading range under this condition, a ferrite sheet is incorporated in the conventional loop antenna. The proposed antenna yields similar reading range with or without metallic environment.
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Design of an X-Band CMOS VCO with a Transformer-Coupled and Transconductance-Boosted Stacked Topology
(2026-06-01)
Peng, Yen Ying
;
Li, Syu Bin
;
Wang, Sen
;
Pakasiri, Chatrpol
This paper presents the design and implementation of an X-band voltage-controlled oscillator (VCO) fabricated in a standard 180-nm CMOS process. To sustain stable oscillation under a constrained power budget, a gm-boosted topology is employed, integrating vertically stacked cross-coupled transistors with a center-tapped transformer to enhance the equivalent negative conductance. The boosting is achieved through two complementary mechanisms: the center-tapped transformer performs an impedance transformation that repurposes the layout parasitic capacitances into transconductance-enhancing elements, while the stacked cross-coupled pair reuses the DC current and suppresses the source-degeneration of a conventional pair, jointly sustaining a robust start-up margin at a low 0.75 V supply. On-wafer measurement results demonstrate a frequency tuning range from 8.78 GHz to 9.13 GHz as the control voltage is swept from 0 V to 1.8 V, with an average VCO gain K<inf>VCO</inf> of 447.5 MHz/V. Under a total DC power consumption of 6.9 mW, the oscillator delivers an output power of 4.54 dBm and exhibits a measured phase noise of −103 dBc/Hz at a 1-MHz offset.
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Dual-band compact wilkinson power divider using common inductor and complex load
(2020-01-01)
Pakasiri, Chatrpol
;
Wang, Sen
A 1.8/2.4-GHz dual-band compact Wilkinson power divider was designed and implemented using an integrated passive device process. The design used a common inductor to match impedance in the even mode. The common inductor replaced two shunt inductors in the circuit so the circuit size was reduced. An additional complex load was then used for matching impedance in the odd mode. The circuit measurements showed reflection at all ports better than -11.9 dB, isolation at the output ports better than -14 dB and transmission coefficient better than -4.3 dB, at both operating frequencies. The circuit occupied only only 0.036λο λ0.018λο at the higher operating frequency at the higher operating frequency.
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Differential Phase Coupler Using Balun-Type Power Divider
(2025-05-01)
Pakasiri, Chatrpol
;
Chang, Chung Yu
;
Wang, Sen
This paper presents a differential phase coupler design methodology in the IPD process. The coupler consists of a balun and two phase-shifter circuits. The compact balun was designed with lumped components and a common inductor. Each output of the balun circuit was connected to a phase shifter with an opposite phase to make a desired output phase. In the design example, a three-port 90-degree hybrid coupler was implemented on the IPD process to operate at the 6 GHz WIFI frequency. The post-simulation showed that all reflection coefficients were below −19 dB, with an insertion loss of 1.76 dB and isolation of 20 dB. The core chip size was only 0.02λ<inf>0</inf> × 0.018λ<inf>0</inf>.
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A 4-bit ultra-wideband complementary metal-oxide-semiconductor attenuator with low root-mean-square amplitude error
(2019-11-01)
Pakasiri, Chatrpol
;
Zhu, Fu Sheng
;
Wang, Sen
This article presents the 4-bit ultra-wideband complementary metal-oxide-semiconductor (CMOS) attenuator in a standard 0.18-μm CMOS process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P<inf>1-dB</inf> considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P<inf>1-dB</inf> is 15 dBm at 5 GHz and the chip area is 1.12 mm2 including all testing pads.

Pakasiri, Chatrpol

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