Pakasiri, Chatrpol

Preferred name

Pakasiri, Chatrpol

Alternative Name

Pakasiri, Charpol

Main Affiliation

Integrated Innovative Technology

chatrpol.pa@kmitl.ac.th

Now showing 1 - 10 of 12

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Impedance Extraction using Impedance Perturbation Method of Electrically Small HF Loop Antenna with Undercover Ferrite Sheet
(2018-12-24)
Mangmisirisap, Kanthiphat
;
Bandudej, Kamorn
;
Pakasiri, Chatrpol
Electrically small high frequency (HF) loop antenna with undercover ferrite sheet yields high radiation resistance for multi-Turn structure. Antenna impedance without radiation differs greatly from that with the radiation effect. Impedance perturbation method is used for extracting antenna impedance with radiation effect at a desired frequency. Matching networks are designed based on the extracted antenna impedance. The measurement results show that the antenna with the designed matching network provides higher return loss.
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Improvement of transmission line circuit on lossy substrate with application on phase shifter design
(2019-03-01)
Pakasiri, Chatrpol
;
Kongchayasukwat, Thitipun
Lumped transmission line circuit design on lossy substrate is studied in this paper. Conventional single section lumped transmission line cannot perform well on lossy substrate as its electrical length gets longer. Multi-section transmission lines can be used to improve transmission line properties in this case. Phase shifter circuits are designed with a large electrical length transmission line. By using a multi-section transmission line, the resulting transmission line properties are better than those of single section transmission line.
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Wireless power transfer system design using electrically small HF loop antennas
(2019-03-01)
Mangmisirisap, Kanthiphat
;
Bandudej, Kamorn
;
Pakasiri, Chatrpol
Wireless power transfer system design with inductive power transfer is proposed in this paper. The system input and output impedances are extracted by using impedance perturbation method. Using matched capacitors, the measured system reflection coefficient magnitude at 13.56 MHz is as low as 0.04 and the transmission coefficient magnitude is at 0.95.
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Study performance of near-field HF antenna using undercover ferrite sheet
(2017-10-19)
Kankhunthod, Kittipon
;
Pakasiri, Chatrpol
A planar loop antennas with and without undercover ferrite are studied in this paper. The field simulated results show that the antenna with undercover ferrite provides more magnetic flux density at the same distance away from it. Using a receiving loop antenna in the simulation, the power gain of both transmitting antennas is compared. By using proper matching networks, the planar loop antenna with undercover ferrite provides a better power gain than that of the planar loop antenna.
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A millimeter-wave in-phase gate-boosting rectifier
(2014-11-01)
Wang, Yu Jiu
;
Liao, I. No
;
Tsai, Chao Han
;
Pakasiri, Chatrpol
This paper introduces a new class of RF-to-dc rectifiers called the in-phase gate-boosting rectifier (IGR). An IGR utilizes an in-phase passive voltage multiplier (IPVM) to boost in-phase V<inf>\rm GS</inf> swing from the driving V<inf>\rm DS</inf> swing. This design simultaneously reduces the effective threshold voltage, forward resistance, and the reverse leakage current of the rectifying transistor. As a consequence, the sensitivity and the efficiency of a high-frequency rectifier can be improved. Furthermore, a C<inf>G</inf>-loaded IPVM presents low input conductance and is shunted with the drains/sources of the rectifying transistors. This makes the realization of the input matching network between the IGR core and the antenna easier, and achieves a higher voltage swing at the input terminals of the IGR core. The criteria, properties, and relating proofs of the IPVM are also discussed. A differential seven-stage millimeter-wave IGR is implemented in a 65-nm RF CMOS process. In this design, an interleaving internal threshold cancellation bias scheme is also introduced to further suppress the power consumption due to biasing circuitry without increasing the layout area. The implemented integrated circuit achieves a state-of-the-art - 7-dBm sensitivity with 20% peak efficiency at 53 GHz and a bandwidth of 10 GHz from 46 to 56 GHz.
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2.4 GHz Rat-Race Coupler with Complex Termination on IPD Process
(2018-12-24)
Pakasiri, Chatrpol
;
Wang, Sen
This paper proposed a rat-race circuit implement on IPD (Integrated Passive Device) process. The termination loads of the circuit have a complex impedance value. Design equations for single frequency operation of distributed structure are provided. Lumped components representation of distributed structure is illustrated in the design example. The measured results yield-5.6 dB reflection coefficient at the input port and-14 dB transmission coefficient at the isolation port. The transmission coefficients at the output ports are better than-7 dB while the phase difference is less than 2 degrees.
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Low-loss and highly-selective differential bandpass filter on integrated passive device process
(2018-04-01)
Pakasiri, Chatrpol
;
Hsu, Keng Chi
;
Wang, Sen
This letter presents a low-loss and highly-selective differential bandpass filter (BPF) with high common-mode rejection ratio (CMRR). The presented integrated passive device process provides high quality lumped elements, and therefore a low insertion loss of the BPF can be obtained. The circuit also uses series-shunt resonators for controlling its differential- and common-mode transmission zeros. Moreover, with a proper choice of circuit component values, a high common-mode rejection can be controlled at a specific frequency without alternating properties of the filter. The chip area of the filter is 3.74 mm<sup>2</sup> including all testing pads. Additionally, the differential BPF achieves a 1.5-dB insertion loss and 11-dB return loss with a 73% 3-dB bandwidth at 2.2 GHz. Finally, the peak CMRR at the frequency of interest is up to 50 dB.
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A Compact 1-5.2 GHz Wideband Low Noise Amplifier
(2019-11-01)
Pakasiri, Chatrpol
;
Yang, Nien Sheng
;
Wang, Sen
A wideband, low noise figure, cascade amplifier is presented in this paper. The proposed low noise amplifier is designed and fabricated in UMC 0.18 μm CMOS technology. In addition, this amplifier uses a resistor-feedback architecture. And this resistor-feedback amplifier contains the PMOS, NMOS and resistors form the amplifier architecture. The measurement results show that for the proposed low noise amplifier, the gain is above 10 dB at the bandwidth of 0.38-5.3 GHz, a maximum P1dB of -15 dB, a minimum NF of 4 dB and operating bands of return loss is greater than 12 dB.
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Improvement of HF RFID reader performance under metallic environment using ferrite sheet
(2017-12-19)
Kankhunthod, Kittipon
;
Lekawat, Lertsak
;
Pakasiri, Charpol
Conventional loop antennas for RFID reader usually perform worse with metallic environment. To improve reading range under this condition, a ferrite sheet is incorporated in the conventional loop antenna. The proposed antenna yields similar reading range with or without metallic environment.
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A 4-bit ultra-wideband complementary metal-oxide-semiconductor attenuator with low root-mean-square amplitude error
(2019-11-01)
Pakasiri, Chatrpol
;
Zhu, Fu Sheng
;
Wang, Sen
This article presents the 4-bit ultra-wideband complementary metal-oxide-semiconductor (CMOS) attenuator in a standard 0.18-μm CMOS process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P<inf>1-dB</inf> considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P<inf>1-dB</inf> is 15 dBm at 5 GHz and the chip area is 1.12 mm<sup>2</sup> including all testing pads.

Pakasiri, Chatrpol

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