Pakasiri, Chatrpol

Preferred name

Pakasiri, Chatrpol

Alternative Name

Pakasiri, Charpol

Main Affiliation

Integrated Innovative Technology

chatrpol.pa@kmitl.ac.th

Now showing 1 - 10 of 14

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Modified Class-F power amplifier design with fundamental frequency output impedance load
(2021-04-01)
Pakasiri, Chatrpol
;
Manasummakij, Prateep
;
Wang, Sen
A modified Class-F power amplifier with medium output power at 433 MHz was designed, simulated and implemented in this paper. The design process used a load condition of 1) output impedance of the amplifier at the fundamental frequency, 2) short-circuit loads at the even harmonics and 3) open-circuit loads at the odd harmonics. By biasing the circuit to be a typical Class-F, the circuit yielded moderate efficiency as the load condition was different from the optimum one. By strongly biasing the circuit toward that of Class-A, the load condition approached the optimum, but the circuit still yielded moderate efficiency due to the low efficiency nature of a Class-A amplifier. By proper choice of the operating point in Class-AB, a prototype circuit, with 9 dBm input power, yielded a maximum PAE of 68.5% with output power 21.8 dBm. Furthermore, at 11 dBm input power, the prototype yielded a better PAE 79.6% with 23.2 dBm output power. Our design procedure did not need expensive load-pull equipment.
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Compact Wilkinson Power Divider Using Composite Right/Left-Handed Transmission Line on CMOS Process
(2020-03-01)
Nithiporndecha, Kittipong
;
Wang, Sen
;
Pakasiri, Chatrpol
This paper shows the design and analysis of CMOS Wilkinson power divider using composite right/left-handed transmission lines. The effects of lossy components in the circuit are also analyzed. The circuit is then implemented on a 0.18-μm CMOS process. The return losses are less than -16 dB, the isolation is better than -26 dB, and the insertion losses are better than -5.15 dB at the frequencies of interest. Its chip size is 0.5 mm2 (9.9e-5λ<inf>o</inf>2) including testing pads.
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A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology
(2024-06-01)
Pakasiri, Chatrpol
;
Hsu, Ke Chung
;
Wang, Sen
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.
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A 10 GHz Compact Balun with Common Inductor on CMOS Process
(2023-01-01)
Pakasiri, Chatrpol
;
Xu, Jian Long
;
Wang, Sen
This paper presents a compact balun with a common inductor design. The design used Wilkinson-type balun topology with modified lumped transmission lines and a common inductor to realize circuit size reduction on a lossy CMOS process. Measurements of the prototype chip had a reflection coefficient below 17.8 dB at all ports, an insertion loss of 1.98 dB, and an isolation of 16.8 dB. The chip size was only 0.025λ<inf>0</inf> × 0.034λ<inf>0</inf>.
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Compact Wilkinson Power Divider with Common Inductor on the IPD Process
(2021-01-01)
Pakasiri, Chatrpol
;
Wang, Sen
This paper presents a Wilkinson power divider using a common inductor. The lumped topology uses the inherently inductive loss of the inductor as a part of the design, so the conventional resistor for high isolation can be omitted. Therefore, low-loss and high-isolation performances of the compact circuit were achieved. The proposed 2.5-GHz divider was implemented on a silicon-based integrated passive device process. Measurement of the prototype chip had a reflection coefficient below 18 dB at all ports, an insertion loss of 0.5 dB and isolation above 28 dB. The chip size is merely 0.011λ o× 0.019λ o.
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A UHF compact complex impedance-transforming balun with high isolation
(2020-01-01)
Nithiporndecha, Kittipong
;
Pakasiri, Chatrpol
Background: A compact complex impedance-transforming balun for UHF frequencies, which is based on a coupled-line structure that matched all ports and provided high output port iso-lation, was designed in this paper. Methods: A lumped component transformation was used to minimize circuit size. The implemented circuit operated at 433 MHz with the reflection coefficients less than-16 dB at all ports, 0.22 dB amplitude balance and 180° phase balance at the output ports. The signal coupling between the output ports was-16.8 dB. The circuit size is small at 0.032λ. Results: Complex impedance-transforming baluns were designed to operate at 433 MHz. The source impedance at port 1 was set at Z<inf>s</inf> = 12-j12Ω and the load impedances at port 2 and 3 were set at Z<inf>L</inf> = 80 + j30Ω. Conclusion: A compact complex impedance-transforming balun at UHF frequency, with all ports matched and high isolations, was designed and illustrated in this paper.
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Modeling a Simple Single-phase Grid-connected Photovoltaic System Using Negative Conductance of Solar Cells
(2023-01-01)
Somdock, Nuttakrit
;
Pakasiri, Chatrpol
;
Sakulkalavek, Aparpron
;
Sirichote, Wichit
This paper presents the simulation of a simple single-phase grid-connected photovoltaic (PV) system using the PSPICE model. The modeling system consists of a PV string, a single-phase current source inverter (CSI), load, and a grid voltage source. The system uses the PV string as the current source. The single-phase CSI was controlled by the grid AC voltage. The operation of the system employs the negative conductance characteristics of the PV string. We studied the voltage and current waveform at the inverter output terminal, the current waveform at the load, the AC power with various open-circuit voltages and temperatures of the PV string. The result showed the current waveform at the inverter output terminal follows the I-V characteristics of the PV string. The current waveform at the load depends on its impedance characteristics. The AC power increased with the open circuit voltage. We found that the maximum efficiency of the AC power conversion system was 63.3% at the peak of the AC voltage source, which was equal to the maximum power voltage of the PV string. In addition, the prototype was built for testing and testing verified the simulation results. The experimental results showed the current waveform at the inverter terminal and load were similar to the simulation results.
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A low-phase-noise and low-power CMOS colpitts VCO using Gm boosting and capacitance switching techniques
(2021-01-01)
Pakasiri, Chatrpol
;
You, Jia Hao
;
Wang, Sen
This letter presents a low-power and low-phase-noise 5-GHz VCO fabricated in a standard CMOS 0.18-μm process. The low power dissipation was achieved by using the PMOS cross-coupled pair and G<inf>m</inf>-boosting topology, and the low phase noise was obtained by adding two pairs of switched capacitor array. The VCO consumed a dc power of 2.92 mW with the supply voltage of 1 V. The measured phase noises were − 104.6 dBc/Hz and − 117.4 dBc/Hz at 1 MHz offset frequency with switched off and on capacitances, respectively, which demonstrated 12.8-dB improvement.
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Simple Class F Power Amplifier Design with Fundamental Frequency Tuning
(2020-03-01)
Manasammakij, Prateep
;
Pongthavornkamol, Tiwat
;
Pakasiri, Chatrpol
Simple class F with medium output power at 433 MHz is designed and simulated in this paper. The design process uses fundamental frequency tuning in find the matching network. At fundamental frequency, the reactance part of the networks needs to be conjugate values of that of the output impedance of the transistor circuit while the resistance part of the network is found by running simulation sweep. The second and third harmonics are also considered in the matching network design. Using the designed matching networks, the amplifiers yield almost optimum efficiency values for input power of 13 and 18 dBm. The proposed technique can save computational costs comparing to load pull technique. In future work it can lead to implementation of a class F power amplifier without using load pull.
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Two CMOS Wilkinson Power Dividers Using High Slow-Wave and Low-Loss Transmission Lines
(2024-08-01)
Pakasiri, Chatrpol
;
Teng, Wei Sen
;
Wang, Sen
This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λ<inf>o</inf>2.

Pakasiri, Chatrpol

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